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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

Hardened Timer/Counter PWM
The MachXO2 EFB contains a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bi-directional, 16-bit Timer/Counter module with independent output compare units and PWM support.

Timer/Counter Registers
The Timer/Counter communicates with the FPGA logic through the WISHBONE interface, by utilizing a set of control, status and data registers. Table 28 shows the register names and their functions. These registers are a subset of the EFB register map. Refer to the EFB register map for specific addresses of each register. Table 28. Timer/Counter Registers
Timer/Counter Register Name TCCR0 TCCR1 TCTOPSET0 TCTOPSET1 TCOCRSET0 TCOCRSET1 TCCR2 TCCNT0 TCCNT1 TCTOP0 TCTOP1 TCOCR0 TCOCR1 TCICR0 TCICR1 TCSR0 TCIRQ TCIRQEN Register Function Control Register 0 Control Register 1 Set Top Counter Value [7:0] Set Top Counter Value [15:8] Set Compare Counter Value [7:0] Set Compare Counter Value [15:8] Control Register 2 Counter Value [7:0] Counter Value [15:8] Current Top Counter Value [7:0] Current Top Counter Value [15:8] Current Compare Counter Value [7:0] Current Compare Top Counter Value [15:8] Current Capture Counter Value [7:0] Current Capture Counter Value [15:8] Status Register Interrupt Request Interrupt Request Enable Address 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F Access Read/Write Read/Write Write Write Write Write Read/Write Read Read Read Read Read Read Read Read Read/Write Read/Write Read/Write

Note: Unless otherwise specified, all Reserved bits in writable registers shall be written ‘0’.

Table 29. Timer/Counter Control 0
TCCR0 Bit Name Default Access 7 RSTEN 0 R/W 6 (Reserved) 0 — 5 0 R/W 4 PRESCALE[2:0] 3 2 CLKEDGE 0 R/W 1 CLKSEL 0 R/W 0x5E 0 (Reserved) 0 R/W

RSTEN

Enables the reset signal (tc_rstn) to enter the Timer/Counter core from the PLD logic. 1: External reset enabled 0: External reset disabled? ? ? ? ? ?

40

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
PRESCALE[2:0] Used to divide the clock input to the Timer/Counter 000: Static (clock disabled) 001: Divide by 1 010: Divide by 8 011: Divide by 64 100: Divide by 256 101: Divide by 1024 110: (Reserved setting) 111: (Reserved setting) Used to select the edge of the input clock source. The Timer/Counter will update states on the edge of the input clock source. 0: Rising Edge 1: Falling Edge Defines the source of the input clock. 0: Clock Tree 1: On-chip Oscillator

CLKEDGE

CLKSEL

Table 30. Timer/Counter Control 1
TCCR1 Bit Name Default Access 7 (Reserved) 0 — 6 SOVFEN 0 R/W 5 ICEN 0 R/W 4 TSEL 0 R/W 3 OCM[1:0] 0 R/W 2 1 TCM[1:0] 0 R/W 0 0x5F

SOVFEN

Enables the overflow flag to be used with the interrupt output signal. It is set when the Timer/Counter is standalone, with no WISHBONE interface. 0: Disabled 1: Enabled Note: When this bit is set, other flags such as the OCRF and ICRF will not be routed to the interrupt output signal.

ICEN

Enables the ability to perform a capture operation of the counter value. Users can assert the “tc_ic” signal and load the counter value onto the TCICR0/1 registers. The captured value can serve as a timer stamp for a specific event. 0: Disabled 1: Enabled Enables the auto-load of the counter with the value from TCTOPSET0/1. When disabled, the value 0xFFFF is auto-loaded. 0: Disabled 1: Enabled Select the function of the output signal of the Timer/Counter. The available functions are Static, Toggle, Set/Clear and Clear/Set. All Timer/Counter modes: 00: The output is static low In non-PWM modes: 01: Toggle on TOP match ? ?

TSEL

OCM[1:0]

41

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
In Fast PWM mode: 10: Clear on TOP match, Set on OCR match 11: Set on TOP match, Clear on OCR match In Phase and Frequency Correct PWM mode: 10: Clear on OCR match when the counter is incrementing Set on OCR match when counter is decrementing 11: Set on OCR match when the counter is incrementing Clear on OCR match when the counter is decrementing TCM[1:0] Timer Counter Mode. Defines the mode of operation for the Timer/Counter. 00: Watchdog Timer Mode 01: Clear Timer on Compare Match Mode 10: Fast PWM Mode 11: Phase and Frequency Correct PWM Mode

Table 31. Timer/Counter Set Top Counter Value 0
TCTOPSET0 Bit Name Default1 Access 1 R/W 1 R/W 1 R/W 7 6 5 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W TCTOPSET[7:0] 0x60

1. Hardware default value may be overridden by EFB component instantiation parameters.

Table 32. Timer/Counter Set Top Counter Value 1
TCTOPSET1 Bit Name Default1 Access 1 R/W 1 R/W 1 R/W 7 6 5 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W TCTOPSET[15:8] 0x61

1. Hardware default value may be overridden by EFB component instantiation parameters.

The value from TCTOPSET0/1 is loaded to the TCTOP0/1 registers once the counter has completed the current counting cycle. Refer to the Timer/Counter Modes of Operation section for usage details. TCTOPSET0 register holds the lower eight bits [7:0] of the top value. TCTOPSET1 register holds the upper eight bits [15:8] of the top value. Table 33. Timer/Counter Set Compare Counter Value 0
TCOCRSET0 Bit Name Default1 Access 1 R/W 1 R/W 1 R/W 7 6 5 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W TCOCRSET[7:0] 0x62

1. Hardware default value may be overridden by EFB component instantiation parameters.

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 34. Timer/Counter Set Compare Counter Value 1
TCOCRSET1 Bit Name Default1 Access 1 R/W 1 R/W 1 R/W 7 6 5 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W TCOCRSET[15:8] 0x63

1. Hardware default value may be overridden by EFB component instantiation parameters.

The value from TCOCRSET0/1 is loaded to the TCOCR0/1 registers once the counter has completed the current counting cycle. Refer to the Timer/Counter Modes of Operation section for usage details. TCOCRSET0 register holds the lower 8-bit value [7:0] of the compare value. TCOCRSET1 register holds the upper 8-bit value[15:8] of the compare value. Table 35. Timer/Counter Control 2
TCCR2 Bit Name Default Access 0 — 0 — 7 6 5 (Reserved) 0 — 0 — 0 — 4 3 2 WBFORCE 0 R/W 1 WBRESET 0 R/W 0 WBPAUSE 0 R/W 0x64

WBFORCE

In non-PWM modes, forces the output of the counter, as if the counter value matched the compare (TCOCR) value or it matched the top value (TCTOP). 0: Disabled 1: Enabled Reset the counter from the WISHBONE interface by writing a '1' to this bit. Manually reset to ‘0’. The rising edge is detected in the WISHBONE clock domain, and the counter is reset synchronously on the next tc_clki. Due to the clock domain crossing, there is a one-clock uncertainty when the reset is effective. This bit has higher priority then WBPAUSE. 0: Disabled 1: Enabled Pause the 16-bit counter 1: Pause 0: Normal

WBRESET

WBPAUSE

Table 36. Timer/Counter Counter Value 0
TCCNT0 Bit Name Default Access 0 R 0 R 0 R 0 R 7 6 5 4 TCCNT[7:0] 0 R 0 R 0 R 0 R 3 2 1 0 0x65

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 37. Timer/Counter Counter Value 1
TCCNT1 Bit Name Default Access 0 R 0 R 0 R 7 6 5 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R TCCNT[15:8] 0x66

Registers TCCNT0 and TCCNT1 are 8-bit registers, which combined, hold the counter value. The WISHBONE host has read-only access to these registers. TCCNT0 register holds the lower 8-bit value [7:0] of the counter value. TCCNT1 register holds the upper 8-bit value [15:8] of the counter value. Table 38. Timer/Counter Current Top Counter Value 0
TCTOP0 Bit Name Default Access 1 R 1 R 1 R 1 R 7 6 5 4 TCTOP[7:0] 1 R 1 R 1 R 1 R 3 2 1 0 0x67

Table 39. Timer/Counter Current Top Counter Value 1
TCTOP1 Bit Name Default Access 1 R 1 R 1 R 7 6 5 4 1 R 3 1 R 2 1 R 1 1 R 0 1 R TCTOP[15:8] 0x68

Registers TCTOP0 and TCTOP1 are 8-bit registers, which combined, receive a 16-bit value from the TCTOPSET0/1. The data stored in these registers represents the top value of the counter. The registers update once the counter has completed the current counting cycle. The WISHBONE host has read-only access to these registers. Refer to the Timer/Counter Modes of Operation section for usage details. TCTOP0 register holds the lower 8-bit value [7:0] of the top value. TCTOP1 register holds the upper 8-bit value [15:8] of the top value. Table 40. Timer/Counter Current Compare Counter Value 0
TCOCR0 Bit Name Default Access 1 R 1 R 1 R 1 R 7 6 5 4 TCOCR[7:0] 1 R 1 R 1 R 1 R 3 2 1 0 0x69

Table 41. Timer/Counter Current Compare Counter Value 1
TCOCR1 Bit Name Default Access 1 R 1 R 1 R 7 6 5 4 1 R 3 1 R 2 1 R 1 1 R 0 1 R TCOCR[15:8] 0x6A

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Registers TCOCR0 and TCOCR1 are 8-bit registers, which combined, receive a 16-bit value from the TCOCRSET0/1. The data stored in these registers represents the compare value of the counter. The registers update once the counter has completed the current counting cycle. The WISHBONE host has read-only access to these registers. Refer to the Timer/Counter Modes of Operation section for usage details. TCOCR0 register holds the lower 8-bit value [7:0] of the compare value. TCOCR1 register holds the upper 8-bit value [15:8] of the compare value. Table 42. Timer/Counter Current Capture Counter Value 0
TCICR0 Bit Name Default Access 0 R 0 R 0 R 0 R 7 6 5 4 TCICR[7:0] 0 R 0 R 0 R 0 R 3 2 1 0 0x6B

Table 43. Timer/Counter Current Capture Counter Value 1
TCICR1 Bit Name Default Access 0 R 0 R 0 R 0 R 7 6 5 4 TCICR[15:8] 0 R 0 R 0 R 0 R 3 2 1 0 0x6C

Registers TCICR0 and TCICR1 are 8-bit registers, which combined, can hold the counter value. The counter value is loaded onto these registers once a trigger event, tc_ic IP signal, is asserted. The capture value is commonly used as a time-stamp for a specific system event. The WISHBONE host has read-only access to these registers. TCICR0 register holds the lower 8-bit value [7:0] of the counter value. TCICR1 register holds the upper 8-bit value [15:8] of the counter value. Table 44. Timer/Counter Status Register
TCSR0 Bit Name Default Access — — — — 7 6 (Reserved) — — — — 5 4 3 BTF 0 R 2 ICRF 0 R 1 OCRF 0 R 0 OVF 0 R 0x6D

BTF

Bottom Flag. Asserted when the counter reaches value zero. A write operation to this register clears this flag. 1: Counter reached zero value 0: Counter has not reached zero Capture Counter Flag. Asserted when the user asserts the TC_IC input signal. The counter value is captured into the TCICR0/1 registers. A write operation to this register clears this flag. This bit is capable of generating an interrupt. 1: TC_IC signal asserted. 0: Normal Compare Match Flag. Asserted when counter matches the TCOCR0/1 register value. A write operation to this register clears this flag. This bit is capable of generating an interrupt. 1: Counter match 0: Normal 45

ICRF

OCRF

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
OVF Overflow Flag. Asserted when the counter matches the TCTOP0/1 register value. A write operation to this register clears this flag. This bit is capable of generating an interrupt. 1: Counter match 0: Normal

Table 45. Timer/Counter Interrupt Status
TCIRQ Bit Name Default Access 0 — 0 — 7 6 5 (Reserved) 0 — 0 — 0 — 4 3 2 IRQICRF 0 R/W 1 IRQOCRF 0 R/W 0 IRQOVF 0 R/W 0x6E

IRQICRF

Interrupt Status for Capture Counter Flag. When enabled, indicates ICRF was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Capture Counter Flag Interrupt 0: No interrupt Interrupt Status for Compare Match Flag. When enabled, indicates OCRF was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Compare Match Flag Interrupt 0: No interrupt Interrupt Status for Overflow Flag. When enabled, indicates OVF was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Overflow Flag Interrupt 0: No interrupt

IRQOCRF

IRQOVF

Table 46. Timer/Counter Interrupt Enable
TCIRQEN Bit Name Default Access 0 — 0 — 7 6 5 (Reserved) 0 — 0 — 0 — 4 3 2 0 R/W 1 0 R/W 0 0 R/W 0x6F IRQICRFEN IRQOCRFEN IRQOVFEN

IRQICRFEN

Interrupt Enable for Capture Counter Flag. 1: Interrupt generation enabled 0: Interrupt generation disabled Interrupt Enable for Compare Match Flag. 1: Interrupt generation enabled 0: Interrupt generation disabled Interrupt Enable for Overflow Flag. 1: Interrupt generation enabled 0: Interrupt generation disabled

IRQOCRFEN

IRQOVFEN

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

Timer Counter Simulation Model
The Timer Counter EFB Register Map translation to the MachXO2 EFB software simulation model is provided below. Table 47. Timer/Counter Simulation Mode
Timer/Counter Register Name TCCR0 RSTEN PRESCALE[2:0] CLKEDGE CLKSEL TCCR1 SOVFEN ICEN TSEL OCM[1:0] TCM[1:0] TCTOPSET0 Register Size/Bit Location [7:0] 7 [5:3] 2 1 [7:0] 6 5 4 [3:2] [1:0] [7:0] Set Top Counter Value [7:0] 0x60 Write Control Register 1 0x5F Register Function Control Register 0 Address 0x5E Access Simulation Model Register Name Simulation Model Register Path ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/

{tc_rstn_ena, tc_gsrn_dis, Read/Write tc_cclk_sel[2:0], tc_sclk_sel[2:0]} tc_rstn_ena tc_cclk_sel[2:0] tc_sclk_sel[2] tc_sclk_sel[1] {1'b0, tc_ovf_ena, tc_ic_ena, Read/Write tc_top_sel, tc_oc_mode[1:0], tc_mode[1:0]} tc_ivf_ena tc_ic_ena tc_top_sel tc_oc_mode[1:0] tc_mode[1:0] {tc_top_set[7], tc_top_set[6], tc_top_set[5], tc_top_set[4], tc_top_set[3], tc_top_set[2], tc_top_set[1], tc_top_set[0]} {tc_top_set[7], tc_top_set[6], tc_top_set[5], tc_top_set[4], tc_top_set[3], tc_top_set[2], tc_top_set[1], tc_top_set[0]}

TCTOPSET[7:0]

[7:0]

../efb_top/efb_pll_sci_inst/u_efb_sci/

TCTOPSET1

[7:0]

Set Top Counter Value [15:8]

0x61

Write

{tc_top_set[15], tc_top_set[14], tc_top_set[13], tc_top_set[12], tc_top_set[11], tc_top_set[10], tc_top_set[9], tc_top_set[8]} {tc_top_set[15], tc_top_set[14], tc_top_set[13], tc_top_set[12], tc_top_set[11], tc_top_set[10], tc_top_set[9], tc_top_set[8]}

../efb_top/efb_pll_sci_inst/u_efb_sci/

TCTOPSET[15:8]

[7:0]

../efb_top/efb_pll_sci_inst/u_efb_sci/

TCOCRSET0

[7:0]

Set Compare Counter Value [7:0]

0x62

Write

{tc_ocr_set[7], tc_ocr_set[6], tc_ocr_set[5], tc_ocr_set[4], tc_ocr_set[3], tc_ocr_set[2], tc_ocr_set[1], tc_ocr_set[0]} {tc_ocr_set[7], tc_ocr_set[6], tc_ocr_set[5], tc_ocr_set[4], tc_ocr_set[3], tc_ocr_set[2], tc_ocr_set[1], tc_ocr_set[0]}

../efb_top/efb_pll_sci_inst/u_efb_sci/

TCOCRSET[7:0]

[7:0]

../efb_top/efb_pll_sci_inst/u_efb_sci/

TCOCRSET1

[7:0]

Set Compare Counter Value [15:8]

0x63

Write

{tc_ocr_set[15], tc_ocr_set[14], tc_ocr_set[13], tc_ocr_set[12], tc_ocr_set[11], tc_ocr_set[10], tc_ocr_set[9], tc_ocr_set[8]} {tc_ocr_set[15], tc_ocr_set[14], tc_ocr_set[13], tc_ocr_set[12], tc_ocr_set[11], tc_ocr_set[10], tc_ocr_set[9], tc_ocr_set[8]}

../efb_top/efb_pll_sci_inst/u_efb_sci/

TCOCRSET[15:8]

[7:0]

../efb_top/efb_pll_sci_inst/u_efb_sci/

TCCR2 WBFORCE WBRESET WBPAUSE TCCNT0 TCCNT[7:0] TCCNT1 TCCNT[15:8] TCTOP0 TCTOP[7:0]

[7:0] 2 1 0 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

Control Register 2

0x64

{1'b0, 1'b0, 1'b0, 1'b0, 1'b0, Read/Write tc_oc_force, tc_cnt_reset, tc_cnt_pause} tc_oc_force tc_cnt_reset tc_cnt_pause

../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/

Counter Value [7:0]

0x65

Read

tc_cnt_sts[7:0] tc_cnt_sts[7:0]

Counter Value [15:8]

0x66

Read

tc_cnt_sts[15:8] tc_cnt_sts[15:8]

Current Top Counter Value [7:0]

0x67

Read

tc_top_sts[7:0] tc_top_sts[7:0]

47

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 47. Timer/Counter Simulation Mode (Continued)
Timer/Counter Register Name TCTOP1 TCTOP[15:8] TCOCR0 TCOCR[7:0] TCOCR1 TCOCR[15:8] TCICR0 TCICR[7:0] TCICR1 TCICR[15:8] TCSR0 BTF ICRF OCRF OVF TCIRQ IRQICRF IRQOCRF IRQOVF TCIRQEN IRQICRFEN IRQOCRFEN IRQOVFEN Register Size/Bit Location [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 3 2 1 0 [7:0] 2 1 0 [7:0] 2 1 0 Interrupt Request Enable 0x6F Interrupt Request 0x6E Status Register 0x6D Read Current Capture Counter Value [15:8] 0x6C Read Current Capture Counter Value [7:0] 0x6B Read Current Compare Top Counter Value [15:8] 0x6A Read Current Compare Counter Value [7:0] 0x69 Read Register Function Current Top Counter Value [15:8] Address 0x68 Access Read Simulation Model Register Name tc_top_sts[15:8] tc_top_sts[15:8] tc_ocr_sts[7:0] tc_ocr_sts[7:0] tc_ocr_sts[15:8] tc_ocr_sts[15:8] tc_icr_sts[7:0] tc_icr_sts[7:0] tc_icr_sts[15:8] tc_icr_sts[15:8] Simulation Model Register Path ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/

{1'b0, 1'b0, 1'b0, 1'b0, tc_btf_sts, ../efb_top/efb_pll_sci_inst/u_efb_sci/ tc_icrf_sts, tc_ocrf_sts, tc_ovf_sts} tc_btf_sts tc_icrf_sts tc_ocrf_sts tc_ovf_sts ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/

{1'b0, 1'b0, 1'b0, 1'b0, 1'b0, Read/Write tc_icrf_irqsts, tc_ocrf_irqsts, tc_ovf_irqsts} tc_icrf_irqsts tc_ocrf_irqsts tc_ovf_irqsts {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, Read/Write tc_icrf_irqena, tc_ocrf_irqena, tc_ovf_irqena} tc_icrf_irqena tc_ocrf_irqena tc_ovf_irqena

Flash Memory (UFM/Configuration) Access
Designers can access the Flash Memory Configuration Logic interface using the JTAG, SPI, I2C, or WISHBONE interfaces. The MachXO2 Flash Memory consists of two sectors: ? User Flash Memory (UFM) — MachXO2-640 and higher density devices provide one sector of User Flash Memory (UFM). ? Configuration — Configuration consists of two sectors Configuration Flash and the Feature Row. The UFM is a Flash sector which is organized in pages. The UFM is not byte addressable. Each page has 128 bits (16 bytes).

48

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide Flash Memory (UFM/Configuration) Access Ports
Designers can access the UFM Sector via JTAG port (compliant with the IEEE 1149.1 and IEEE 1532 specifications), external Slave SPI port and external I2C Primary port and the internal WISHBONE interface of the EFB module. Figure 29 illustrates the interfaces to the UFM and Configuration Memory sectors. Figure 29. Interfaces to the UFM/Configuration Sectors
Flash Memory
Configuration (including UFM USERCODE) Feature Row (including TraceID)

Flash Command Interface
Configuration Slave

JTAG

WISHBONE Interface

EFB Register Map

Primary I2C Port (Address yyyxxxxx00)

User Logic

EFB
Configuration Master/Slave
SPI Port ufm_sn

The configuration logic arbitrates access from the interfaces by the following priority. When higher priority ports are enabled Flash Memory access by lower priority ports will be blocked. 1. 2. 3. 4. JTAG Port Slave SPI Port I2C Primary Port WISHBONE Slave Interface

Note: Enabling Flash Memory (UFM/Configuration) Interface using Enable Configuration Interface command 0x74 Transparent Mode will temporarily disable certain features of the device including: ? Power Controller ? GSR ? Hardened User SPI port ? Hardened User Primary I2C port Functionality is restored after the Flash Memory (UFM/Configuration) Interface is disabled using Disable Configuration Interface command 0x26 followed by Bypass command 0xFF.

49

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide Flash Memory (UFM/Configuration) Access through WISHBONE Slave Interface
The WISHBONE Slave interface of the EFB module enables designers to access the Flash Memory (UFM/Configuration) directly from the FPGA core logic. The WISHBONE bus signals, described earlier in this document, are utilized by a WISHBONE host that designers can implement using the general purpose FPGA resources. In addition to the WISHBONE bus signals, an interrupt request output signal is brought to the FPGA fabric. The IP signal is “wbc_ufm_irq”, and it functions as an interrupt request to the internal WISHBONE host, based on the data Read/Write FIFO status or arbitration error. Note: To access the Flash Memory (UFM/Configuration) via WISHBONE in R1 devices, the hard SPI port or the primary I2C port must be enabled. For more details, refer to AN8086, Designing for Migration from MachXO2-1200R1 to Standard (Non-R1) Devices. The WISHBONE Interface communicates to the Configuration Logic through a set of data, control and status registers. Table 48 shows the register names and their functions. These registers are a subset of the EFB register map. Refer to the EFB register map for specific addresses of each register. Table 48. WISHBONE to Flash Memory (CFG) Logic Registers
WISHBONE to CFG Register Name CFGCR CFGTXDR CFGSR CFGRXDR CFGIRQ CFGIRQEN Register Function Control Transmit Data Status Receive Data Interrupt Request Interrupt Request Enable Address 0x70 0x71 0x72 0x73 0x74 0x75 Access Read/Write Write Read Read Read/Write Read/Write

Note: Unless otherwise specified, all Reserved bits in writable registers shall be written ‘0’.

Table 49. Flash Memory (UFM/Configuration) Control
CFGCR Bit Name Default Access 7 WBCE 0 R/W 6 RSTE 0 R/W 0 — 0 — 0 — 5 4 3 (Reserved) 0 — 0 — 0 — 2 1 0 0x70

WBCE

WISHBONE Connection Enable. Enables the WISHBONE to establish the read/write connection to the Flash Memory (UFM/Configuration) logic. This bit must be set prior to executing any command through the WISHBONE port. Likewise, this bit must be cleared to terminate the command. See “Command and Data Transfers to Flash Memory (UFM/Configuration) Space” on page 54 for more information on framing WISHBONE commands. 1: Enabled 0: Disabled WISHBONE Connection Reset. Resets the input/output FIFO logic. The reset logic is level sensitive. After setting this bit to '1' it must be cleared to '0' for normal operation. 1: Reset 0: Normal operation

RSTE

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Table 50. Flash Memory (UFM/Configuration) Transmit Data
CFGTXDR Bit Name Default Access 0 W 0 W 0 W 7 6 5 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W CFG_Transmit_Data[7:0] 0x71

CFG_Transmit_Data[7:0]

CFG Transmit Data. This register holds the byte that will be written to the Flash Memory (UFM/Configuration) logic. Bit 0 is LSB.

Figure 30. Flash Memory (UFM/Configuration) Status
CFGSR Bit Name Default Access 7 WBCACT 0 R 6 (Reserved) 0 — 5 TXFE 0 R 4 TXFF 0 R 3 RXFE 0 R 2 RXFF 0 R 1 SSPIACT 0 R 0 I2CACT 0 R 0x72

WBCACT

WISHBONE Bus to Configuration Logic Active. Indicates that the WISHBONE to configuration interface is active and the connection is established. 1: WISHBONE Active 0: WISHBONE not Active Transmit FIFO Empty. Indicates that the Transmit Data register is empty. This bit is capable of generating an interrupt. 1: FIFO empty 0: FIFO not empty Transmit FIFO Full. Indicates that the Transmit Data register is full. This bit is capable of generating an interrupt. 1: FIFO full 0: FIFO not full Receive FIFO Empty. Indicates that the Receive Data register is empty. This bit is capable of generating an interrupt. 1: FIFO empty 0: FIFO not empty Receive FIFO Full. Indicates that the Transmit Data register is full. This bit is capable of generating an interrupt. 1: FIFO full 0: FIFO not full Slave SPI Active. Indicates the Slave SPI port has started actively communicating with the Configuration Logic while WBCE was enabled. This port has priority over the I2C and WISHBONE ports and will preempt any existing, and prohibit any new, lower priority transaction. This bit is capable of generating an interrupt. 1: Slave SPI port active 0: Slave SPI port not active? ? ?

TXFE

TXFF

RXFE

RXFF

SSPIACT

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I2CACT I2C Active. Indicates the I2C port has started actively communicating with the Configuration Logic while WBCE was enabled. This port has priority over the WISHBONE ports and will preempt any existing, and prohibit any new WISHBONE transaction. This bit is capable of generating an interrupt. 1: I2C port active 0: I2C port not active

Table 51. Flash Memory (UFM/Configuration) Receive Data
CFGRXDR Bit Name Default Access 0 R 0 R 0 R 7 6 5 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R CFG_Receive_Data[7:0] 0x73

CFG_Receive_Data[7:0]

CFG Receive Data. This register holds the byte read from the Flash Memory (UFM/Configuration) logic. Bit 0 in this register is LSB.

Table 52. Flash Memory (UFM/Configuration) Interrupt Status
CFGIRQ Bit Name Default Access 0 — 7 (Reserved) 0 — 6 5 IRQTXFE 0 R/W 4 IRQTXFF 0 R/W 3 IRQRXFE 0 R/W 2 IRQRXFF 0 R/W 1 0 R/W 0 0 R/W 0x74 IRQSSPIACT IRQI2CACT

IRQTXFE

Interrupt Status for Transmit FIFO Empty. When enabled, indicates TXFE was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Transmit FIFO Empty Interrupt 0: No interrupt Interrupt Status for Transmit FIFO Full. When enabled, indicates TXFF was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Transmit FIFO Full Interrupt 0: No interrupt Interrupt Status for Receive FIFO Empty. When enabled, indicates RXFE was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Receive FIFO Empty Interrupt 0: No interrupt Interrupt Status for Receive FIFO Full. When enabled, indicates RXFF was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Receive FIFO Full Interrupt 0: No interrupt? ? ? ?

IRQTXFF

IRQRXFE

IRQRXFF

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IRQSSPIACT Interrupt Status for Slave SPI Active. When enabled, indicates SSPIACT was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Slave SPI Active Interrupt 0: No interrupt Interrupt Status for I2C Active. When enabled, indicates I2CACT was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: I2C Active Interrupt 0: No interrupt

IRQI2CACT

Table 53. Flash Memory (UFM/Configuration) Interrupt Enable
CFGIRQEN Bit Name Default Access 7 0 — 6 0 — 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W (Reserved) 0x75 IRQTXFEEN IRQTXFFEN IRQRXFEEN IRQRXFFEN IRQSSPIACTEN IRQI2CACTEN

IRQTXFEEN

Interrupt Enable for Transmit FIFO Empty 1: Interrupt generation enabled 0: Interrupt generation disabled Interrupt Enable for Transmit FIFO Full 1: Interrupt generation enabled 0: Interrupt generation disabled Interrupt Enable for Receive FIFO Empty 1: Interrupt generation enabled 0: Interrupt generation disabled Interrupt Enable for Receive FIFO Full 1: Interrupt generation enabled 0: Interrupt generation disabled Interrupt Enable for Slave SPI Active 1: Interrupt generation enabled 0: Interrupt generation disabled Interrupt Enable for I2C Active 1: Interrupt generation enabled 0: Interrupt generation disabled

IRQTXFFEN

IRQRXFEEN

IRQRXFFEN

IRQSSPIACTEN

IRQI2CACTEN

Table 54. Unused (Reserved) Register
UNUSED Bit Name Default Access 0 — 0 — 0 — 0 — 7 6 5 4 (Reserved) 0 — 0 — 0 — 0 — 3 2 1 0 0x76

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Table 55. EFB Interrupt Source
EFBIRQ Bit Name Default Access 0 R 7 6 (Reserved) 0 R 0 R 5 4 UFMCFG_INT 0 R 3 TC_INT 0 R 2 SPI_INT 0 R 1 I2C2_INT 0 R 0 I2C1_INT 0 R 0x77

UFMCFG_INT

Flash Memory (UFM/Configuration) Interrupt Source. Indicates EFB interrupt source is from the UFM/Configuration Block. Use CFGIRQ for further source resolution. 1: A bit is set in register CFGIRQ 0: No interrupt Timer/Counter Interrupt Source. Indicates EFB interrupt source is from the Timer/Counter Block. Use TCIRQ for further source resolution. 1: A bit is set in register TCIRQ 0: No interrupt SPI Interrupt Source. Indicates EFB interrupt source is from the SPI Block. Use SPIIRQ for further source resolution. 1: A bit is set in register SPIIRQ 0: No interrupt I2C2 Interrupt Source. Indicates EFB interrupt source is from the Secondary I2C Block. Use I2C_2_ IRQ for further source resolution. 1: A bit is set in register I2C_2_ IRQ 0: No interrupt I2C1 Interrupt Source. Indicates EFB interrupt source is from the Primary I2C Block. Use I2C_1_ IRQ for further source resolution. 1: A bit is set in register I2C_1_ IRQ 0: No interrupt? ?

TC_INT

SPI_INT

I2C2_INT

I2C1_INT

Command and Data Transfers to Flash Memory (UFM/Configuration) Space
The command and data transfers to the Flash Memory (UFM/Configuration) are identical for all the access ports, regardless of their different physical interfaces. The Flash Memory (UFM/Configuration) is organized in pages. Therefore, users address a specific page for Read or Write operations to that page. Each page has 128 bits (16 bytes). The transfers are based on a set of instructions and page addresses. The Flash memory is composed of two sectors, Configuration Memory (sector 0) and UFM (sector 1). The Erase operations are sector based.

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Table 56. UFM (Sector 1) Commands
Command Name Read Status Register Check Busy Flag Bypass Command MSB LSB 0x3C 0xF0 0xFF SVF Command Name LSC_READ_STATUS LSC_CHECK_BUSY ISC_NOOP Description Read the 4-byte Configuration Status Register Read the Configuration Busy Flag status Null operation. Enable Transparent UFM access – All user I/Os (except the hardened user SPI and primary user I2C ports) are governed by the user logic, the device remains in User mode. (The subsequent commands in this table require the interface to be enabled.) Enable Offline UFM access – All user I/Os (except persisted sysCONFIG ports) are tristated. User logic ceases to function, UFM remains accessible, and the device enters 'Offline' access mode. (The subsequent commands in this table require the interface to be enabled.) Disable the configuration (UFM) access. Set the UFM sector 14-bit Address Register Reset the address to point to Sector 1, Page 0 of the UFM. Read the UFM data. Operand specifies number of pages to read. Address Register is postincremented. Erase the UFM sector only. Write one page of data to the UFM. Address Register is post-incremented.

Enable Configuration Interface (Transparent Mode)

0x74

ISC_ENABLE_X

Enable Configuration Interface (Offline Mode)

0xC6

ISC_ENABLE

Disable Configuration Interface Set Address Reset UFM Address Read UFM Erase UFM Program UFM Page

0x26 0xB4 0x47 0xCA 0xCB 0xC9

ISC_DISABLE LSC_WRITE_ADDRESS LSC_INIT_ADDR_UFM LSC_READ_TAG LSC_ERASE_TAG LSC_PROG_TAG

Table 57. Configuration Flash (Sector 0) Commands
Command Name Read Device ID Read USERCODE Read Status Register Read Busy Flag Refresh
1

Command MSB LSB 0xE0 0xC0 0x3C 0xF0 0x79 0x7D 0xFF

SVF Command Name IDCODE_PUB USERCODE LSC_READ_STATUS LSC_CHECK_BUSY LSC_REFRESH LSC_DEVICE_CTRL ISC_NOOP

Description Read the 4-byte Device ID (0x01 2b 20 43). Read 32-bit USERCODE. Read the 4-byte Configuration Status Register. Read the Configuration Busy Flag status. Launch boot sequence (same as toggling PROGRAMN pin). Triggers the Power Controller to enter or wake from standby mode. Null operation. Enable Transparent Configuration Flash access – All user I/Os (except the hardened user SPI and primary user I2C ports) are governed by the user logic, the device remains in User mode. (The subsequent commands in this table require the interface to be enabled.)

STANDBY Bypass

Enable Configuration Interface (Transparent Mode)

0x74

ISC_ENABLE_X

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Table 57. Configuration Flash (Sector 0) Commands (Continued)
Command Name Command MSB LSB SVF Command Name Description Enable Offline Configuration Flash access – All user I/Os (except persisted sysCONFIG ports) are tri-stated. User logic ceases to function, UFM remains accessible, and the device enters ‘Offline’ access mode. (The subsequent commands in this table require the interface to be enabled.) Exit access mode. Set the Configuration Flash 14-bit Page Address. Verify device ID with 32-bit input, set Fail flag if mismatched. Reset the address to point to Sector 0, Page 0 of the Configuration Flash. Read the Flash data. Operand specifies number of pages to read. Address Register is postincremented. Erase the Config Flash, FEATURE Row, FEABITs, Done bit, Security bits and USERCODE. Write 1 page of data to the Flash Memory (Configuration/UFM). Address Register is post-incremented. Program the Done bit. Program the Security bit (Secures CFG Flash sector). Program the Security Plus bit (Secures CFG and UFM Sectors). Note: SECURITY and SECURITY PLUS commands are mutually exclusive. Read Feature Row. Program Feature Row. Read FEA bits. Program the FEA bits.

Enable Configuration Interface (Offline Mode)

0xC6

ISC_ENABLE

Disable Configuration Interface Set Configuration Flash Address Verify Device ID Reset Configuration Flash Address Read Flash

0x26 0xB4 0xE2 0x46 0x73

ISC_DISABLE LSC_WRITE_ADDRESS VERIFY_ID LSC_INIT_ADDRESS LSC_READ_INCR_NV

Erase

0x0E

ISC_ERASE

Program Page Program DONE Program SECURITY

0x70 0x5E 0xCE

LSC_PROG_INCR_NV ISC_PROGRAM_DONE ISC_PROGRAM_SECURITY

Program SECURITY PLUS Program USERCODE Read Feature Row Program Feature Row Read FEABITS Program FEABITs

0xCF 0xC2 0xE7 0xE4 0xFB 0xF8

ISC_PROGRAM_SECPLUS

ISC_PROGRAM_USERCODE Program 32-bit USERCODE. LSC_READ_FEATURE LSC_PROG_FEATURE LSC_READ_FEABITS LSC_PROG_FEABITS

1. The Refresh commands are not supported by the software simulation model.

Table 58. Non-Volatile Register (NVR) Commands
Command Name Read Trace ID code Command msb lsb 0x19 SVF Command Name UIDCODE_PUB Description Read 64-bit TraceID.

When using the WISHBONE bus interface, the commands, operand and data are written to the CFGTXDR Register. The Slave SPI or I2C interface shift the most significant bit (MSB) first into the MachXO2 device. This is required only when communicating with the configuration logic inside the MachXO2 device. In order to perform a Write, Read or Erase operation with the UFM or Configuration Flash, it is required that the interface is enabled using Command 0x74. Affected commands are noted in the Command Description as “EN Required.” Once the modification operations are completed, the interface can be disabled using commands 0x26 and 0xFF.

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Table 59. Erase Flash (0x0E)
UFM x CFG x NVR EN Required Y CMD (Hex) 0E Operands (Hex) See below Data Mode — Data Size — Data Format —

Operand: where:

0000 ucfs 0000 0000 0000 0000(binary) u: Erase UFM sector 0: No action 1: Erase c: Erase CFG sector (Config Flash, DONE, security bits, USERCODE) 0: No action 1: Erase Erase Feature sector (Slave I2C address, sysCONFIG port persistence, Boot mode, etc.) 0: No action 1: Erase Erase SRAM 0: No action 1: Erase

f:

s:

Notes:

Poll the BUSY bit (or wait, see Table 99) after issuing this command for erasure to complete before issuing a subsequent command other than Read Status or Check Busy. Erased condition for Flash bits = 0

Examples:

0x0E 04 00 00 Erase CFG sector 0x0E 08 00 00 Erase UFM sector 0x0E 0C 00 00 Erase UFM and CFG sectors

Table 60. Read TraceID Code (0x19)
UFM CFG NVR x EN Required N CMD (Hex) 19 Operands (Hex) 00 00 00 Data Mode R Data Size 8B Data Format —

Example: Note:

0x19 00 00 00 Read 8-byte TraceID First byte read is user portion. Next seven bytes are unique to each silicon die.

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Table 61. Disable Configuration Interface (0x26)
UFM x CFG x NVR EN Required — CMD (Hex) 26 Operands (Hex) 00 00 Data Mode — Data Size — Data Format —

Example:

0x26 00 00 Disable Flash Memory (UFM/configuration) interface for change access

Notes:

Must have only two operands The interface cannot be disabled while the Configuration Status Register Busy bit is asserted. After commands (for example, Erase, Program) verify Busy is clear before issuing the Disable command. This command should be followed by Command 0xFF (BYPASS) to complete the Disable operation. The BYPASS command is required to restore Power Controller, GSR, Hardened User SPI and I2C port operation. SRAM must be erased before exiting Offline (0xC6) Mode

Table 62. Read Status Register (0x3C)
UFM x CFG x NVR EN Required N CMD (Hex) 3C Operands (Hex) 00 00 00 Data Mode R Data Size 4B Data Format (Binary) xxxx IxEE Exxx xxxx xxFB xxCD xxxx xxxx

Data Format:

EEE

Most significant byte of SR is received first, LSB last. D bit 8 Flash or SRAM Done Flag? When C = 0 SRAM Done bit has been programmed? ? D = 1 Successful Flash to SRAM transfer ? D = 0 Failure in the Flash to SRAM transfer When C=1 Flash Done bit has been programed ? D = 1 Programmed ? D = 0 Not Programmed C bit 9 Enable Configuration Interface (1=Enable, 0=Disable) B bit 12: Busy Flag (1 = busy) F bit 13: Fail Flag (1 = operation failed) I I=0 Device verified correct, I=1 Device failed to verify bits[25:23]: Configuration Check Status 000: No Error 001: ID ERR 010: CMD ERR 011: CRC ERR 100: Preamble ERR 101: Abort ERR 110: Overflow ERR 111: SDM EOF (all other bits reserved) The BUSY bit should be checked following all Enable, Erase or Program operations. Wait at least 1us after power-up or asserting wb_rst_i before accessing the EFB. 0x3C 00 00 00 Read 4-byte Status Register for example, 0x00 00 20 00 (fail flag set) 58

Usage: Note: Example:

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 63. Reset CFG Address (0x46)
UFM CFG x NVR EN Required Y CMD (Hex) 46 Operands (Hex) 00 00 00 Data Mode — Data Size — Data Format —

Example:

0x46 00 00 00 Set Address register to Configuration Sector 0, page 0

Table 64. Reset UFM Address (0x47)
UFM x CFG NVR EN Required Y CMD (Hex) 47 Operands (Hex) 00 00 00 Data Mode — Data Size — Data Format —

Example:

0x47 00 00 00 Set Address register to UFM Sector 1, page 0

Table 65. Program DONE (0x5E)
UFM CFG x NVR EN Required Y CMD (Hex) 5E Operands (Hex) 00 00 00 Data Mode — Data Size — Data Format —

Example: Note:

0x5E 00 00 00 Set the DONE bit Poll the BUSY bit (or wait 200us) after issuing this command for programming to complete before issuing a subsequent command other than Read Status or Check Busy.

Table 66. Program Configuration Flash (0x70)
UFM CFG x NVR EN Required Y CMD (Hex) 70 Operands (Hex) 00 00 01 Data Mode W Data Size 16B Data Format 16 bytes UFM write data

Example:

0x70 00 00 01 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Write one page of data, pointed to by Address Register

Notes:

16 data bytes must be written following the command and operand bytes to ensure proper data alignment. The Address Register is auto-incremented following the page write. Operands (0x00 00 00) are equivalent to (0x00 00 01). Use 0x0E to erase CFG sector prior to executing this command. Poll the BUSY bit (or wait 200us) after issuing this command for programming to complete before issuing a subsequent command other than Read Status or Check Busy.

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Table 67. Read Configuration Flash (0x73) (SPI)
UFM CFG x NVR EN Required Y CMD (Hex) 73 Operands (Hex) * (below) Data Mode R Data Size ** (below) Data Format *** (below)

Note: *Operand:

This applies when Configuration Flash is read through SPI 0001 0000 00pp pppp pppp pppp (binary) pp..pp: num_pages Number of CFG pages to read when num_pages = 1 Number of CFG pages to read +1 when num_pages > 1 (num_pages * 16) bytes Read CFG may be aborted at any time. Any data remaining in the read FIFO will be discarded. Any read data beyond the prescribed read size will be indeterminate. The Address Register is auto-incremented after each page read. 0x73 10 00 01 0 bytes dummy followed by one page of CFG data (16 bytes total) 0x73 10 00 04 Read 1 page dummy followed by three pages of CFG data (four pages total)

**Data Size: Note:

***Examples:

Table 68. Read Configuration Flash (0x73) (I2C/SPI)
UFM CFG x NVR EN Required Y CMD (Hex) 73 Operands (Hex) * (below) Data Mode R Data Size ** (below) Data Format *** (below)

Note: *Operand:

This applies when Configuration Flash is read through I2C or SPI 0000 0000 00pp pppp pppp pppp (binary) pp..pp: num_pages Number of CFG pages to read when num_pages = 1 Number of CFG pages to read +1 when num_pages > 1 (num_pages * 16) bytes 32 bytes + (num_pages) * (16 + 4) bytes when num_pages=1 when num_pages>1

**Data Size: Note:

Read CFG may be aborted at any time. Any data remaining in the read FIFO will be discarded. Any read data beyond the prescribed read size will be indeterminate. The Address Register is auto-incremented after each page read. 0x73 00 00 01 0 bytes dummy followed by one page CFG data (16 bytes total) 0x73 00 00 04 Read 2 pages dummy, followed by three sets [1 page CFG data, followed by four bytes dummy] (five pages and 12 dummy bytes total)

***Examples:

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Table 69. Read Configuration Flash (0x73) (WISHBONE)
UFM CFG x NVR EN Required Y CMD (Hex) 73 Operands (Hex) * (below) Data Mode R Data Size ** (below) Data Format *** (below)

Note: *Operand:

This applies when Configuration Flash is read through WISHBONE 0000 0000 00pp pppp pppp pppp (binary) pp..pp: num_pages Number of CFG pages to read when num_pages = 1 Number of CFG pages to read +1 when 1 < num_pages ≤ 12? Set to 0x3FFF when num_pages > 12 (num_pages * 16) bytes 32 bytes + (num_pages) * (16 + 4) bytes when num_pages=1 when num_pages>1

**Data Size: Note:

When reading more than 12 pages, the num_pages argument is intentionally oversized. It is not necessary to read the extra pages. Read CFG may be aborted at any time. Any data remaining in the read FIFO will be discarded. Any read data beyond the prescribed read size will be indeterminate. The Address Register is auto-incremented after each page read. 0x73 00 00 01 0 bytes dummy followed by one page CFG data (16 bytes total) 0x73 00 00 04 Read 2 pages dummy, followed by three sets [1 page CFG data, followed by four bytes dummy] (five pages and 12 dummy bytes total)

***Examples:

Note:

The maximum speed which one page of data (num_page=1) can be read using WISHBONE and no wait states is 16.6 MHz. Faster WISHBONE clock speeds are supported by inserting WB wait states to observe the retrieval delay timing requirement. For more information, refer to the Reading Flash Pages section of TN1204, MachXO2 Programming and Configuration Usage Guide.

Table 70. Enable Configuration Interface (Transparent) (0x74)
UFM x CFG x NVR EN Required — CMD (Hex) 74 Operands (Hex) 08 00 00 or 08 00 Data Mode — Data Size — Data Format —

Notes:

The I2C interface uses only two operands all other interfaces use three operands. This command is required to enable modification of the UFM, configuration Flash, or nonvolatile registers (NVR). Terminate this command with command 0x26 followed by command 0xFF. Exercising this command will temporarily disable certain features of the device, notably GSR, user SPI port, primary user I2C port and Power Controller. These features are restored when the command is terminated. Poll the BUSY bit (or wait 5us) after issuing this command for the Flash pumps to fully charge.

Example:

0x74 08 00 00 Enable UFM/configuration interface for change access through a non-I2C interface.

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Table 71. Refresh (0x79)
EN Required CMD (Hex) 79 Operands (Hex) 00 00 Data Format (Binary) —

UFM

CFG

NVR

Data Mode —

Data Size —

Example: Note:

0x79 00 00 Issue Refresh command The Refresh command will Launch Boot sequence Must have only two operands After completing the Refresh command (for example, SPI SN deassertion or I2C stop), further bus accesses are prohibited for the duration of tREFRESH. Violating this requirement will cause the Refresh process to abort and leave the MachXO2 device in an unprogrammed state. Occasionally, following a device REFRESH or PROGRAMN pin toggle, the secondary I2C port may be left in an undefined (non-idle) state. The likely hood of this condition is design and route dependent. To positively return the Secondary I2C port to the idle state, write a value of 0x44 to register I2C_2_CMDR via WISHBONE immediately after device reset is released. This will cause a short low-pulse on SCK as the hardblock signals a STOP on the bus then returns to the idle state. Failure to manually return the Secondary I2C port to the idle state may result in an I2C bus lock-up condition. Normal I2C activity can be commenced without additional delay.

Table 72. STANDBY (0x7D)
UFM CFG x NVR EN Required N CMD (Hex) 7D Operands (Hex) 0y 00 Data Mode — Data Size — Data Format (Binary) —

Example:

0x7D 0y 00 y:2 Triggers the Power Controller to enter standby mode y:8 Triggers the Power Controller to wakeup from standby mode Must have only two operands. The MachXO2 Power Controller needs to be included in the design. Additionally the following can be used to trigger the Power Controller to wakeup from standby mode (if the user logic standby signal has not been enabled): 1. I2C has the following ways: a. Primary I2C Configuration port – Address match to the I2C Configuration address (No other settings required) b. Primary or Secondary I2C User port – Address match the I2C User address. Must have I2C_1_CR[WKUPEN] or I2C_1_CR[WKUPEN] set c. General Call – Send the General Call Wakeup command (0xF3). Must have General Calls enabled (I2C_1_CR[GCEN] or I2C_2_CR[GCEN] set) and use the General Call address SPI from the assertion of either Slave Configuration (ufm_sn) or User (spi_scsn) chip select, as long as the appropriate control register bit is set: a. Configuration: SPICR1[WKUPEN_CFG] b. User: SPICR[WKUPEN_USER]

Notes:

2.

For more information on the Power Controller refer to TN1198, Power Estimation and Management for MachXO2 Devices.

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Table 73. Set Address (0xB4)
UFM x CFG x EN NVR Required Y CMD (Hex) B4 Operands (Hex) 00 00 00 Data Mode W Data Size 4B Data Format (Binary) 0s00 0000 0000 0000 00aa aaaa aaaa aaaa

Data Format:

s:

sector 0: Configuration 1: UFM

aa..aa:address14-bit page address Example: 0xB4 00 00 00 40 00 00 0A Set Address register to UFM sector, page 10 decimal

Table 74. Read USERCODE (0xC0)
UFM CFG x NVR EN Required Y/N CMD (Hex) C0 Operands (Hex) 00 00 00 Data Mode R Data Size 4B Data Format (Hex) —

Example:

0xC0 00 00 00? EN Required = Y EN Required = N

Read 4-byte USERCODE from CFG sector? Read 4-byte USERCODE from SRAM

Table 75. Program USERCODE (0xC2)
UFM CFG x NVR EN Required Y CMD (Hex) C2 Operands (Hex) 00 00 00 Data Mode W Data Size 4B Data Format (Hex) —

Example: Note:

0xC2 00 00 00 10 20 30 40 Sets USERCODE with 32-bit input 0x10 20 30 40 Poll the BUSY bit (or wait 200us) after issuing this command for programming to complete before issuing a subsequent command other than Read Status or Check Busy.

Table 76. Enable Configuration Interface (Offline) (0xC6)
UFM CFG x NVR EN Required CMD (Hex) C6 Operands (Hex) 0y 00 00 Data Mode — Data Size — Data Format —

Operand:

08 00 00 - Enable Flash Normal mode. Normal edit mode for Offline configuration. Used for all offline commands described in this document, including Erase SRAM. 00 00 00 - Enable SRAM mode. Optional edit mode. Supports Erase SRAM command only.

Example: Notes:

0xC6 08 00 00 Enable Flash Memory (UFM/configuration) interface for offline change access. Use this command to enable offline modification of the UFM, Configuration Flash, or non-volatile registers (NVR). SRAM must be erased exiting Offline mode. When exiting Offline mode follow the command 0x26 with the command 0xFF. Exercising this

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command will tri-state all user I/Os (except persisted sysCONFIG ports). User logic ceases to function. UFM remains accessible. Poll the BUSY bit (or wait 5us) after issuing this command for the Flash pumps to fully charge. Table 77. Program UFM (0xC9)
UFM x CFG NVR EN Required CMD (Hex) Y C9 Operands (Hex) 00 00 01 Data Mode W Data Size 16B Data Format 16 bytes UFM write data

Example: Notes:

0xC9 00 00 01 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Write one page of data, pointed to by Address Register 16 data bytes must be written following the command and operand bytes to ensure proper data alignment. The Address Register is auto-incremented following the page write. Use 0x0E or 0xCB to erase UFM sector prior to executing this command. Poll the BUSY bit (or wait 200us) after issuing this command for programming to complete before issuing a subsequent command other than Read Status or Check Busy.

Table 78. Read UFM (0xCA) (SPI)
UFM x CFG NVR EN Required Y CMD (Hex) CA Operands (Hex) *(below) Data Mode R Data Size **(below) Data Format ***(below)

*Operand: where: **Data Size Note:

0001 0000 00pp pppp pppp pppp (binary) pp..pp: num_pages Number of CFG pages to read when num_pages = 1 Number of CFG pages to read +1 when num_pages > 1

(num_pages * 16) bytes Read UFM may be aborted at any time. Any data remaining in the read fifo will be discarded. Any read data beyond the prescribed read size will be indeterminate. The Address Register is auto-incremented after each page read. 0xCA 10 00 01 Read 0 bytes dummy followed by one page UFM data (16 bytes total) 0xCA 10 00 04 Read one page dummy followed by three pages UFM data (four pages total)

***Examples:

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Table 79. Read UFM (0xCA) (I2C/SPI)
UFM x CFG NVR EN Required Y CMD (Hex) CA Operands (Hex) *(below) Data Mode R Data Size **(below) Data Format ***(below)

*Operand: where: **Data Size: Note:

0000 0000 00pp pppp pppp pppp (binary) pp..pp: num_pages Number of CFG pages to read when num_pages = 1 Number of CFG pages to read +1 when num_pages > 1 when num_pages=1 when num_pages>1

(num_pages * 16) bytes 32 bytes + (num_pages * 16 + 4) bytes

Read UFM may be aborted at any time. Any data remaining in the read fifo will be discarded. Any read data beyond the prescribed read size will be indeterminate. The Address Register is auto-incremented after each page read. 0xCA 00 00 01 Read 0 bytes dummy followed by one page UFM data (16 bytes total) 0xCA 00 00 04 Read two pages dummy followed by three sets [one page UFM data, followed by four bytes dummy] (five pages total and 12 dummy bytes)

***Examples:

Table 80. Read UFM (0xCA) (WISHBONE)
UFM x CFG NVR EN Required Y CMD (Hex) CA Operands (Hex) *(below) Data Mode R Data Size **(below) Data Format ***(below)

*Operand: where:

0000 0000 00pp pppp pppp pppp (binary) pp..pp: num_pages Number of CFG pages to read when num_pages = 1 Number of CFG pages to read +1 when 1 < num_pages ≤ 12? Set to 0x3FFF when num_pages > 12 when num_pages=1 when num_pages>1

**Data Size: Note:

(num_pages * 16) bytes 32 bytes + (num_pages * 16 + 4) bytes

When reading more than 12 pages, the num_pages argument is intentionally oversized. It is not necessary to read the extra pages. Read UFM may be aborted at any time. Any data remaining in the read fifo will be discarded. Any read data beyond the prescribed read size will be indeterminate. The Address Register is auto-incremented after each page read. 0xCA 00 00 01 Read 0 bytes dummy followed by one page UFM data (16 bytes total) 0xCA 00 00 04 Read two pages dummy followed by three sets [one page UFM data, followed by four bytes dummy] (five pages total and 12 dummy bytes)

***Examples:

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Note: The maximum WISHBONE clock speed with which one page of data (num_page=1) can be read using WISHBONE and no wait states is 16.6 MHz. Faster WISHBONE clock speeds are supported by inserting WB wait states to observe the retrieval delay timing requirement. For more information, refer to the Reading Flash Pages section of TN1204, MachXO2 Programming and Configuration Usage Guide.

Table 81. Erase UFM (0xCB)
UFM x CFG NVR EN Required Y CMD (Hex) CB Operands (Hex) 00 00 00 Data Mode — Data Size — Data Format —

Notes:

Erased condition for UFM bits = ‘0’ Poll the BUSY bit (or wait, see Table 99) after issuing this command for erasure to complete before issuing a subsequent command other than Read Status or Check Busy.

Example:

0xCB 00 00 00 Erase UFM sector

Table 82. Program SECURITY (0xCE)
UFM CFG x NVR EN Required Y CMD (Hex) CE Operands (Hex) 00 00 00 Data Mode — Data Size — Data Format —

Example:

0xCE 00 00 00 Set the SECURITY bit

Note:

Poll the BUSY bit (or wait 200us) after issuing this command for programming to complete before issuing a subsequent command other than Read Status or Check Busy. SECURITY and SECURITY PLUS commands are mutually exclusive.

Table 83. Program SECURITY PLUS (0xCF)
UFM CFG x NVR EN Required Y CMD (Hex) CF Operands (Hex) 00 00 00 Data Mode — Data Size — Data Format —

Example: Note:

0xCF 00 00 00 Set the SECURITY PLUS bit Poll the BUSY bit (or wait 200us) after issuing this command for programming to complete before issuing a subsequent command other than Read Status or Check Busy. SECURITY and SECURITY PLUS commands are mutually exclusive.

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Table 84. Read Device ID Code (0xE0)
UFM CFG x NVR EN Required N CMD (Hex) E0 Operands (Hex) 00 00 00 Data Mode R Data Size 4B Data Format (Hex) See Table 85

Example: Table 85. Device ID Table

0xE0 00 00 00 Read 4-byte device ID

Device Name MachXO2-256 MachXO2-640 MachXO2-1200/MachXO2-640U MachXO2-2000/MachXO2-1200U MachXO2-4000/MachXO2-2000U MachXO2-7000

HE/ZE Devices 0x01 2B 00 43 0x01 2B 10 43 0x01 2B 20 43 0x01 2B 30 43 0x01 2B 40 43 0x01 2B 50 43

HC Devices 0x01 2B 80 43 0x01 2B 90 43 0x01 2B A0 43 0x01 2B B0 43 0x01 2B C0 43 0x01 2B D0 43

Example:

0xE0 00 00 00 Read 4-byte device ID

Table 86. Verify Device ID Code (0xE2)
UFM CFG x NVR EN Required Y CMD (Hex) E2 Operands (Hex) 00 00 00 Data Mode W Data Size 4B Data Format (Hex) See Table 85

Example:

0xE2 00 00 00 01 2B 20 43 Verify device ID with 32-bit input, sets ID Error bit 27 in SR if mismatched

Table 87. Program Feature Row (0xE4)
UFM CFG NVR EN Required Y CMD (Hex) E4 Operands (Hex) 00 00 00 Data Mode Data Size 8B Data Format (Hex) 00 00 ss uu cc cc cc cc

Data Format:

ss: 8 bits for the user programmable I2C Slave Address uu: 8 bits for the user programmable TraceID cc cc cc cc: 32 bits of Custom ID code It is not recommended to reprogram the Feature Row in system as it should be programmed ideally once during manufacturing. 0xE4 00 00 00 00 00 01 00 00 00 12 34 Program Feature Row with User I2C address set to 1, default user TraceID string, Custom ID code of 12 34

Note: Example:

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 88. Read Feature Row (0xE7)
UFM CFG NVR x EN Required Y CMD (Hex) E7 Operands (Hex) 00 00 00 Data Mode R Data Size 8B Data Format (Hex) 00 00 ss uu cc cc cc cc

Data Format:

ss: uu: cc cc cc cc:

8 bits for the user programmable I2C Slave Address 8 bits for the user programmable TraceID 32 bits of Custom ID code

Example:

0xE7 00 00 00 Reads the Feature Row

Table 89. Check Busy Flag (0xF0)
UFM x CFG x NVR EN Required N CMD (Hex) F0 Operands (Hex) 00 00 00 Data Mode R Data Size 1B Data Format (Binary) Bxxx xxxx

Data Format: Example:

B: bit 7: Busy Flag (1= busy) (all other bits reserved) 0xF0 00 00 00 Read one byte, for example, 0x80 (busy flag set)

Table 90. Program FEABITs (0xF8)
UFM CFG NVR x EN Required Y CMD (Hex) F8 Operands (Hex) 00 00 00 Data Mode W Data Size 2B Data Format (Binary) 00 bb mi sj di pa 00 00

Data Format:

bb:

Boot Sequence 1. If b=00 (Default) and m=0 then Single Boot from Configuration Flash 2. If b=00 and m=1 then Dual Boot from Configuration Flash then External if there is a failure 3. If b=01 and m=1 then Single Boot from External Flash Master SPI Port Persistence 0=Disabled (Default), 1=Enabled I2C Port Persistence 0=Enabled (Default), 1=Disabled Slave SPI Port Persistence 0=Enabled (Default), 1=Disabled JTAG Port Persistence 0=Enabled (Default), 1=Disabled DONE Persistence 0=Disabled (Default), 1=Enabled INITN Persistence 0=Disabled (Default), 1=Enabled

m: i: s: j: d: i:

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
p: a: Note: Example: PROGRAMN Persistence 0=Enabled (Default), 1=Disabled my_ASSP Enabled 0=Disabled (Default), 1=Enabled

It is not recommended to reprogram the FEABITs in system as it should be programmed ideally once during manufacturing. 0xF8 00 00 00 0D 20 Programs the FEABITs

Table 91. Read FEABITs (0xFB)
UFM CFG NVR x EN Required Y CMD (Hex) FB Operands (Hex) 00 00 00 Data Mode R Data Size 2B Data Format (Binary) 00 bb mi sj di pa 00 00

Data Format:

bb:

Boot Sequence 1. If b=00 (Default) and m=0 then Single Boot from Configuration Flash 2. If b=00 and m=1 then Dual Boot from Configuration Flash then External if there is a failure 3. If b=01 and m=1 then Single Boot from External Flash Master SPI Port Persistence 0=Disabled (Default), 1=Enabled I2C Port Persistence 0=Enabled (Default), 1=Disabled Slave SPI Port Persistence 0=Enabled (Default), 1=Disabled JTAG Port Persistence 0=Enabled (Default), 1=Disabled DONE Persistence 0=Disabled (Default), 1=Enabled INITN Persistence 0=Disabled (Default), 1=Enabled PROGRAMN Persistence 0=Enabled (Default), 1=Disabled my_ASSP Enabled 0=Disabled (Default), 1=Enabled

m: i: s: j: d: i: p: a:

Table 92. Bypass (Null Operation) (0xFF)
UFM x CFG x NVR x EN Required N CMD (Hex) FF Operands (Hex) FF FF FF Data Mode — Data Size — Data Format (Binary) —

Note: Example:

Operands are optional 0xFF FF FF FF Bypass

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Interface to Configuration Flash
The WISHBONE interface of the EFB module allows a WISHBONE host to access the configuration resources of the MachXO2 devices. This can be particularly useful for reading data from configuration resources such as USERCODE and TraceID. Most importantly, this feature allows users to update the Configuration Flash array of the devices while the device is in operation mode. This is a self-configuration operation. Upon power-up or a configuration refresh operation, the new content of the Configuration Flash is loaded into the Configuration SRAM and the device continues operation with a new configuration. The data transfer and execution of operations is the same as the one documented in the UFM section of this document. This is due to the fact that the UFM is also a Flash Memory resource and the communication between the WISHBONE host and the configuration logic is performed through the same command, status and data registers. Please see Tables 48 to 95 for information on these registers. Figure 31 shows a basic flow diagram for implementing a Configuration Flash Update initiated via any of the sysCONFIG ports (I2C, SPI, or WISHBONE). For detailed information on MachXO2 programming and configuration, see TN1204, MachXO2 Programming and Configuration Usage Guide.

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Figure 31. Basic Configuration Flash Update Example
Start

Ensure unused Configuration Ports are Inactive

Enable Transparent Configuration (0x74)

Wait for !BUSY (0xF0) then verify !FAIL (0x3C)

Set Flash DONE bit (0x5E)

Erase Configuration Flash Sector (0x0E)

(optional) Set USERCODE (0xC2) Set SECURITY (0xCE, 0xCF)

Wait for !BUSY (0xF0) then verify !FAIL (0x3C)

Wait for !BUSY (0xF0) then verify !FAIL (0x3C)

Set Address to 0 (0x46)

Disable Configuration (0x26)

Write 1 Page Config Data (0x70)

Issue REFRESH (0x79)

N

Wait for !BUSY (0xF0) then verify !FAIL (0x3C)

Configure via WISHBONE? N N Wait for tREFRESH then verify DONE (0x3C)

Y

Write more data?

Y

Done

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Command Framing
I2C Framing
Each command string sent to the I2C EFB port must be correctly “framed” using the protocol defined for each interface. In the case of I2C, the protocol is well known and defined by the industry as shown below. Table 93. Command Framing Protocol, by Interface
Interface Pre-op (+) Start Command String (Command/Operands/Data) Post-op (-) Stop

IC

2

Figure 32. I2C Read Device ID Example
SCL SDA
Start By Master Frame 1 I C Slave Address Byte
2

...
A6 A5 A4 A3 A2 0 0 W 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

...
ACK By MachXO2

ACK By MachXO2 Frame 2 CMD Byte

ACK By MachXO2 Frame 3 Op Byte 1

SCL (continued) SDA (continued) 0 0 0 0 0 0 0 0 0
ACK By MachXO2 Frame 4 Op Byte 2 Frame 5 Op Byte 3

... 0 0 0 0 0 0 0
ACK By MachXO2

...

SCL (continued) SDA (continued)
Restart By Master Frame 6 I C Slave Address Byte
2

...
A6 A5 A4 A3 A2 0 0 R 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1

...
ACK By Master

ACK By MachXO2 Frame 7 Read ID Byte 1

ACK By Master Frame 8 Read ID Byte 2

SCL (continued) SDA (continued)
ID ID ID ID

0

0

0

0
ACK By Master

0

1

0

0

0

0

1

1
NACK By Master Stop By Master

Frame 9 Read ID Byte 3

Frame 10 Read ID Byte 4

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide SPI Framing
Each command string sent to the SPI EFB port must be correctly ‘framed’ using the protocol defined for each interface. In the case of SSPI the protocol is well known and defined by the industry as shown below: Table 94. Command Framing Protocol, by Interface
Interface SPI Pre-op (+) Assert CS Command String (Command/Operands/Data) Post-op (-) De-assert CS

Figure 33. SSPI Read Device ID Example
SCSN SPI_SCK MOSI MISO
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

... ... ... ...

CMD Byte

Op Byte 1

Op Byte 2

SCSN (continued) SPI_SCK (continued) MOSI (continued) MISO (continued)
Op Byte 3 0 0 0 0 0 0 0 0

... ... ... ...

0

0

0

0

0

0

0

1

0

0

1

0

1

0

1

1

Read ID Byte 1

Read ID Byte 2

SCSN (continued) SPI_SCK (continued) MOSI (continued) MISO (continued)
ID ID ID ID 0 0 0 0 0 1 0 0 0 0 1 1

Read ID Byte 3

Read ID Byte 4

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide WISHBONE Framing
To access the Flash Memory (UFM/Configuration) each command string sent to the WISHBONE EFB ports must be correctly ‘framed’ using the protocol defined for each interface. In the case of the internal WISHBONE port, each command string is preceded by setting CFGCR[WBCE]. Similarly, each command string is followed by clearing the CFGCR[WBCE] bit. Table 95. Command Framing Protocol, by Interface
Interface WISHBONE Pre-op (+) Assert CFGCR[WBCE] Command String (Command/Operands/Data) Post-op (-) De-assert CFGCR[WBCE]

Figure 34. WISHBONE Read Device ID Example (-1200 HC Device)
wb_clk_i wb_we_i wb_adr_i wb_dat_i wb_dat_o wb_str_i wb_ack_o 70 80 71 E0 71 00 71 00 71 00 01 2B A0 43 73 73 73 73 70 00

UFM Write and Read Examples
The UFM and Configuration sectors support page-oriented read and write operations while erase operations are sector-based. Consistent with many Flash memory devices, byte-oriented operations are not supported. Also, as typical with Flash memory devices, attempting to modify a previously written location in Flash requires a read-modify-write operation on the smallest erasable Flash unit. In the case of MachXO2, the smallest erasable unit is the entire UFM sector or the entire Configuration Sector. For example, to arbitrarily modify a byte value in the UFM, the user must: 1. 2. 3. 4. Read and save all UFM data to an alternate location (for example, EBR); Erase the UFM sector; Modify the selected byte; and Program the UFM page by page.

In some applications it may be appropriate to keep a working copy of the UFM contents in volatile Embedded Block RAM and update the non-volatile UFM at appropriate intervals. The following examples show the sequence of commands for writing and reading from UFM. Table 96. Write Two UFM Pages
Instruction Number 1 R/W1 W CMD2 + 74 + 2 W 3C 00 00 00 — Poll Configuration Status Register 08 00 00 — Operand Data Open frame Enable Configuration Interface Close frame Comment

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Table 96. Write Two UFM Pages (Continued)
Instruction Number R/W1 R + 3 W 47 + 4 W C9 + 5 W R + 6 W C9 + 7 W R + 8 W 26 + 9 W FF 1. When accessing UFM/Configuration Flash via WISHBONE use CFGTXDR (0x71) to write data and CFDRXDR (0x73) to read data. 2. ‘+’ and ‘-’ refer to the command framing protocol appropriate for the interface, discussed in “Command Framing” on page 72.

CMD2

Operand

Data xx xx bx xx

Comment (Repeat until Busy Flag not set, or wait 5us if not polling)

00 00 00



Init UFM Address to 0000

00 00 01

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

Write UFM Page 0 Data

3C

00 00 00

— xx xx bx xx

Poll Configuration Status Register (repeat until Busy Flag not set, or wait 200us if not polling)

00 00 01

10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F

Write UFM Page 1 Data (Note: Address automatically incremented)

3C

00 00 00

— xx xx bx xx

Poll Configuration Status Register (poll until Busy Flag clear, or wait 200us if not polling)

00 00



Disable Configuration Interface





Bypass (NOP)

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 97. Read One UFM Page (All Devices, WISHBONE/SPI)
Instruction Number 1 R/W1 W CMD2 + 74 + 2 W R + 3 W B4 + 4 W R + 5 W 26 + 6 W FF 1. When accessing UFM/Configuration Flash via WISHBONE use CFGTXDR (0x71) to write data and CFDRXDR (0x73) to read data. 2. ‘+’ and ‘-’ refer to the command framing protocol appropriate for the interface, discussed in “Command Framing” on page 72.

Operand 08 00 00

Data Open frame —

Comment Enable Configuration Interface Close frame

3C

00 00 00

— xx xx bx xx

Poll Configuration Status Register (Repeat until Busy Flag not set, or wait 5us if not polling)

00 00 00

40 00 00 01

Set UFM Address to 0001

CA

10 00 01 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F

Read one page UFM (page 1) data

00 00



Disable Configuration Interface





Bypass (NOP)

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 98. Read Two UFM Pages (WISHBONE/SPI)
Instruction Number 1 R/W1 W CMD2 + 74 + 2 W R + 3 W 47 + 4 W CA 10 00 03 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F + 5 W 26 + 6 W FF 1. When accessing UFM/Configuration Flash via WISHBONE use CFGTXDR (0x71) to write data and CFDRXDR (0x73) to read data. 2. ‘+’ and ‘-’ refer to the command framing protocol appropriate for the interface 3. num_pages count must include dummy page.

Operand 08 00 00

Data Open frame —

Comment Enable Configuration Interface Close frame

3C

00 00 00

— xx xx bx xx

Poll Configuration Status Register (Repeat until Busy Flag not set, or wait 5us if not polling)

00 00 00



Init UFM address to 0000

Read two pages of UFM data, after one page of dummy bytes.3

R

00 00



Disable Configuration Interface





Bypass (NOP)

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Flash Memory Erase and Program Performance
Table 99. Flash Memory (UFM/Configuration) Performance in MachXO2 Devices1
MachXO2 MachXO2 MachXO2 MachXO2 MachXO2 MachXO2 MachXO2 MachXO2 MachXO2 -256 -640 -640U -1200 -1200U -2000 -2000U -4000 -7000 CFG Erase (tEraseCFG) Min. Max. 400 700 130 0.2 — — — — 9000 600 1100 270 0.2 300 600 40 0.2 12000 800 1400 500 0.2 400 700 110 0.2 15000 800 1400 500 0.2 400 700 110 0.2 15000 1100 1900 740 0.2 500 900 140 0.2 15000 1100 1900 740 0.2 500 900 140 0.2 15000 1800 3100 1400 0.2 600 1000 180 0.2 30000 1800 3100 1400 0.2 600 1000 180 0.2 30000 2800 4800 2200 0.2 900 1600 480 0.2 30000

CFG Program All (tProgramCFG) 1 page UFM Erase (tEraseUFM) Min. Max.

UFM Program All (tProgramUFM) 1 page tErase (max) Note 2

1. All times are averages, in (ms). SRAM erase times are < 0.1 ms. 2. tErase (max) is recommended for algorithm based time-outs.

Erase/Program/Verify Time Calculation Example
Using the data above, it is possible to roughly calculate the time required to perform an Erase/Program/Verify operation. The calculation assumes nearly 100% bus utilization. Overhead required by bus master processes, if any, is not accounted for in the equation below. E/P/V time (?s): where: tEraseProgramVerify = tErase + tProgram + tVerify tErase = tEraseCFG + tEraseUFM1 tProgram = 0.2 ?s * number of Pages to program2 tVerify = (8 * number of Pages programmed) * BusEff * tBUSCLK

Table 100. E/P/V Calculation parameters
BusEff (Single Page Read) I2C SPI WB 14 12 5.25 BusEff3 (Multi Page Read) >12 >8 >3 tBUSCLK 2.5us min 0.015us min 0.020us min

1. Sector erase times are additive. If a sector (for example, CFG) is not erased, its erase time is 0. 2. Data transfer time is insignificant to tProgram for high-speed data protocols. To account for slow bus speeds (for example, I2C) multiply tVerify by 2. 3. Bus efficiency approaches this value as number of read pages increases.

Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.

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Revision History
Date November 2016 Version 2.4 Change Summary Corrected figure reference in Table 9, I2C Status (Primary/Secondary). Corrected Read UFM description in Table 56, UFM (Sector 1) Commands. Corrected Read Flash description in Table 57, Configuration Flash (Sector 0) Commands. Updated document per Product Bulletin PB1381.

— Updated Table 67, Read Configuration Flash (0x73) (SPI). — Updated Table 68, Read Configuration Flash (0x73) (I2C/SPI). — Added Table 69, Read Configuration Flash (0x73) (WISHBONE). — Updated Table 78, Read UFM (0xCA) (SPI). — Updated Table 79, Read UFM (0xCA) (I2C/SPI). — Added Table 80, Read UFM (0xCA) (WISHBONE).
March 2016 2.3 Updated WISHBONE Read Cycle section. Added information on avoiding simulation mismatch in functional simulations. Updated I2C Registers section. Modified Figure 6, I2C Master Read/Write Example (via WISHBONE). Updated Flash Memory Erase and Program Performance section. Added tErase (max) values to Table 99, Flash Memory (UFM/Configuration) Performance in MachXO2 Devices. September 2015 2.2 Updated I2C Registers section. Modified description of RARC and TROE. Updated SPI Registers section. Modified description of TXEDGE and CPOL. Updated SPI Timing Diagrams section. Corrected the following diagrams: — Figure 24, SPI Control Timing (SPICR2[CPHA]=0, SPICR1[TXEDGE]=0) — Figure 25, SPI Control Timing (SPICR2[CPHA]=1, SPICR1[TXEDGE]=0) — Figure 26, SPI Control Timing (SPICR2[CPHA]=0, SPICR1[TXEDGE]=1) — Figure 27, SPI Control Timing (SPICR2[CPHA]=1, SPICR1[TXEDGE]=1) Updated Flash Memory (UFM/Configuration) Access Ports section. Added disabled feature in Note. Updated Command Framing section. Corrected device name in Figure 32, I2C Read Device ID Example. Updated Technical Support Assistance section.

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Date February 2015 Version 2.1 Change Summary Updated WISBONE Bus Interface section. Revised In Table 2, WISHBONE Slave Interface Signals of the EFB Module. Added details to the wb_clk_i signal name description. Updated Hardened I2C IP Cores section. Added new EFB instantiation requirement for I2C configuration port access per Product Bulletin PB1412. Updated I2C Registers section. — Changed Figure 6, I2C Master Read/Write Example (via WISHBONE). — Revised SDA_DEL_SEL[1:0] description. Updated SPI Registers section. Corrected CPOL description. Updated SPI Timing Diagrams section. Changed the following figures: — Figure 24, SPI Control Timing (SPICR2[CPHA]=0, SPICR1[TXEDGE]=0) — Figure 25, SPI Control Timing (SPICR2[CPHA]=1, SPICR1[TXEDGE]=0) — Figure 26, SPI Control Timing (SPICR2[CPHA]=0, SPICR1[TXEDGE]=1) — Figure 27, SPI Control Timing (SPICR2[CPHA]=1, SPICR1[TXEDGE]=1) November 2014 2.0 Updated I2C Registers section. Added note to SRW description under Table 9, I2C Status (Primary/Secondary). Updated Table 57, Configuration Flash (Sector 0) Commands. Updated Erase command description. Updated Command Descriptions by Command Code section.

— Updated information on Erase Feature sector under Table 59, Erase
Flash (0x0E).

— Updated note under Table 85, Program Feature Row (0xE4) — Updated note under Table 88, Program FEABITs (0xF8).
June 2014 1.9 Updated the following figures: — Figure 17-24, SPI Control Timing (SPICR2[CPHA]=0, SPICR1[TXEDGE]=0) — Figure 17-25, SPI Control Timing (SPICR2[CPHA]=1, SPICR1[TXEDGE]=0) — Figure 17-26, SPI Control Timing (SPICR2[CPHA]=0, SPICR1[TXEDGE]=1) — Figure 17-27, SPI Control Timing (SPICR2[CPHA]=1, SPICR1[TXEDGE]=1). Updated Table 69, Read Configuration Flash (0x73) (I2C/WISHBONE/SPI). Revised Data Size formatting when num_pages>1. Updated Figure 17-2. Updated Figure 17-4. Updated Figure 17-5. Updated Figure 17-26. Corrected version 01.5 Revision History. 01.7 Updated Table 17-69, Enable Configuration Interface (Transparent) (0x74). Changed Operands (Hex) data and added information to Notes and Example sections. Updated Table 17-97, Flash Memory (UFM/Configuration) Performance in MachXO2 Devices. Updated Erase/Program/Verify equation in Erase/Program/Verify Time Calculation Example section.

February 2014 January 2014

01.8 01.6

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Date December 2013 Version 01.5 Updated Figure 17-2. Added Typical I2C Transactions section. Added and reorganized Command Framing section. Moved I2C Framing section under Command Framing section. Added Figure 17-18. Added Typical SPI Transactions section. Moved SPI Framing section under Command Framing section. Changed Operands (Hex) value in Table 17-75 and added description. Moved WISHBONE Framing section under Command Framing section. Moved Flash Memory Erase and Program Performance and Erase/Program/Verify Time Calculation Example sections after UFM Write and Read Examples section. Changed CPOL = 1 description in SPI Registers section. Updated Figure 17-23. Changed second instance of SPISR[TRDY] to SPISR[ROE]. Updated Figure 17-24. September 2013 01.4 Updated CPOL definition in the SPI Registers section. Changed SCK idle state from low to high. Updated SPI Control Timing figures in the SPI Timing Diagrams section. Corrected 0xCA num_pages and Data Size. Removed I2C Clock-Stretching feature per PCN #10A-13. Updated the following figures: Change Summary

— I2C Master Read/Write Example (via WISHBONE) — I2C Slave Read/Write Example (via WISHBONE) — EFB Master – I2C Write — EFB Master – I2C Read
Corrected I2C General Call Data Register (Primary/Secondary) table number. Updated Technical Support Assistance information April 2013 01.3 Read Configuration Flash (0x73) (I2C/WISHBONE/SPI) table – Corrected table title. Read Feature Row (0xE7) table – Updated Data Format in the table and description. Updated information in the I2C Master Read/Write Example (via WISHBONE) figure. Updated examples in the Read UFM (0xCA) (WISHBONE/SPI/I2C) table. Added note: SECURITY and SECURITY PLUS commands are mutually exclusive. Added Erase/Program/Verify time calculation example. Updated (decreased) the maximum WISHBONE clock rate for page reads from 36 MHz to 16.6 MHz. Corrected BUSY wait times (1000ns -> 200ns) in Write Two UFM Pages table. Updated Basic Configuration Flash Update Example, changed "Wait for !BUSY" to "Wait for tREFRESH" in last step. Added Wait for tREFRESH caution to Refresh command description. Clarified Secondary I2C non-idle reset issue after REFRESH.

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Date October 2012 Version 01.2 Change Summary Added restriction: Primary port can be used as Configuration/UFM port or as a user port, but not both. Added restriction: Primary I2C port is unavailable while in ISC_ENABLE_X (transparent) configuration access mode. August 2012 01.1 Timer/Counter Control 1 table – Corrected names of four LSBs. Program Feature Row (0xE4) table – Updated Data Size and Data Format (Hex) columns and text below table for ss, uu and cc cc cc cc. Added example. Read Feature Row (0xE7) table – Updated CMD (Hex) column. Read FEABITs (0xFB) table – Removed example below table. Read USERCODE (0xC0) table – Data Size column updated. EN Required” value changed from “N” to “Y/N” and example text updated. Updated Timer/Counter Control 0 table and Timer/Counter Control 1 table. Updated Basic Configuration Flash Update Example diagram. Device ID Table – Updated Device Name column. Read Status Register (0x3C) table – Updated Data Format column. Verify Device ID Code (0xE2) table – “EN Required” value changed from “N” to “Y” and example text updated. June 2012 01.0 Initial release.

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