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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
November 2016 Technical Note TN1246

Introduction
This reference guide supplements TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2? Devices Usage Guide which explains the software usage. In this document you will find: ? WISHBONE Protocol ? EFB Register Map ? Command Sequences ? Examples As an overview, the MachXO2 FPGA family combines a high-performance, low power, FPGA fabric with built-in, hardened control functions and on-chip User Flash Memory (UFM). The hardened control functions ease design implementation and save general purpose resources such as LUTs, registers, clocks and routing. The hardened control functions are physically located in the Embedded Function Block (EFB). All MachXO2 devices include an EFB module. The EFB block includes the following control functions: ? Two I2C Cores ? One SPI Core ? One 16-bit Timer/Counter ? Interface to Flash Memory which includes: — User Flash Memory for MachXO2-640 and higher densities — Configuration Logic ? Interface to Dynamic PLL configuration settings ? Interface to On-chip Power Controller through I2C and SPI

? 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

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TN1246_2.4

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Figure 1 shows the EFB architecture and the interface to the FPGA core logic. Figure 1. Embedded Function Block (EFB)
Flash Memory
Configuration (including UFM USERCODE) Feature Row (including TraceID)

Flash Command Interface Configuration Slave EFB Register Map
OR

JTAG Primary I2C Port

WISHBONE Interface

User Master/Slave User Master/Slave EFB Configuration Master/Slave User Master/Slave Timer/ Counter

User Logic

Secondary I2C Port

SPI Port

User Logic

PLL0/ PLL1

Power Controller

EFB Register Map
The EFB module has a Register Map to allow the service of the hardened functions through the WISHBONE bus interface read/write operations. Each hardened function has dedicated 8-bit Data and Control registers, with the exception of the Flash Memory (UFM/Configuration), which are accessed through the same set of registers. Table 1 documents the register map of the EFB module. The PLL registers are located in the MachXO2 PLL modules, but they are accessed through EFB WISHBONE read/write cycles. Table 1. EFB Register Map
Address (Hex) 0x00-0x1F 0x20-0x3F 0x40-0x49 0x4A-0x53 0x54-0x5D 0x5E-0x6F 0x70-0x75 0x76-0x77 Hardened Function PLL0 Dynamic Access1 PLL1 Dynamic Access1 I2C Primary I2C Secondary SPI Timer/Counter Flash Memory (UFM/Configuration) EFB Interrupt Source

1. There can be up to two PLLs in a MachXO2 device. PLL0 has an address range from 0x00 to 0x1F. PLL1 (if present) has an address range from 0x20 to 0x3F. ? Reference TN1199, MachXO2 sysCLOCK PLL Design and Usage Guide, for details on PLL configuration registers and recommended usage.

Address spaces that are not defined in Table 1 are invalid and will result in non-deterministic results. It is the responsibility of the designer to ensure valid addresses are presented to the EFB WISHBONE slave interface.

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide WISBONE Bus Interface
The WISHBONE Bus in the MachXO2 is compliant with the WISHBONE standard from OpenCores. It provides connectivity between FPGA user logic and the EFB functional blocks. The user can implement a WISHBONE Master interface to interact with the EFB WISHBONE slave interface or a LatticeMico8? soft processor core can be used to interact with the EFB WISHBONE. The block diagram in Figure 2 shows the supported WISHBONE bus signals between the FPGA core and the EFB. Table 2 provides a detailed definition of the supported signals. Figure 2. WISHBONE Bus Interface Between the FPGA Core and the EFB Module
MachXO2

WISHBONE Master (User Logic)

wb_clk_i wb_rst_i wb_cyc_i wb_stb_i wb_we_i wb_addr_i[7:0] wb_dat_i[7:0] wb_dat_o[7:0] wb_ack_o

WISHBONE Slave Interface

User Logic

EFB Register Map

EFB

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 2. WISHBONE Slave Interface Signals of the EFB Module
Signal Name wb_clk_i I/O Input Width 1 Description Positive edge clock used by WISHBONE Interface registers and hardened functions within the EFB module. Supports clock speeds up to 133 MHz. When used in conjunction with the I2C User Slave or Configuration Slave ports, the clock speed must be at least 7.5x the I2C bus speed (for example, >3.0 MHz when I2C rate = 400 kHz). Active-high, synchronous reset signal that will only reset the WISHBONE interface logic. This signal will not affect the contents of any registers. It will only affect ongoing bus transactions. Wait 1us after de-assertion before starting any subsequent WISHBONE transactions. Active-high signal, asserted by the WISHBONE master, indicates a valid bus cycle is present on the bus. Active-high strobe, input signal, indicating the WISHBONE slave is the target for the current transaction on the bus. The EFB module asserts an acknowledgment in response to the assertion of the strobe. Level sensitive Write/Read control signal. Low indicates a Read operation, and High indicates a Write operation. 8-bit wide address used to select a specific register from the register map of the EFB module. 8-bit input data path used to write a byte of data to a specific register in the register map of the EFB module. 8-bit output data path used to read a byte of data from a specific register in the register map of the EFB module. Active-high, transfer acknowledge signal asserted by the EFB module, indicating the requested transfer is acknowledged.

wb_rst_i

Input

1

wb_cyc_i wb_stb_i wb_we_i wb_adr_i wb_dat_i wb_dat_o wb_ack_o

Input Input Input Input Input Output Output

1 1 1 8 8 8 1

To interface to the EFB you must create a WISHBONE Master controller in the User Logic. In a multiple-Master configuration, the WISHBONE Master outputs are multiplexed in a user-defined arbiter. A LatticeMico8 soft processor can also be utilized along with the Mico System Builder (MSB) platform which can implement multi-Master bus configurations. If two Masters request the bus in the same cycle, only the outputs of the arbitration winner reach the Slave interface. The EFB WISHBONE bus supports the “Classic” version of the WISHBONE standard. Given that the WISHBONE bus is an open source standard, not all features of the standard are implemented or required: ? Tags are not supported in the WISHBONE Slave interface of the EFB module. Given that the EFB is a hardened block, these signals cannot be added by the user. ? The Slave WISHBONE bus interface of the EFB module does not require the byte select signals (sel_i or sel_o), since the data bus is only a single byte wide. ? The EFB WISHBONE slave interface does not support the optional error and retry access termination signals. If the slave receives an access to an invalid address, it will simply respond by asserting wb_ack_o signal. It is the responsibility of the user to stay within the valid address range.

WISHBONE Write Cycle
Figure 3 shows the waveform of a Write cycle from the perspective of the EFB WISHBONE Slave interface. During a single Write cycle, only one byte of data is written to the EFB block from the WISHBONE Master. A Write operation requires a minimum three clock cycles. On clock Edge 0, the Master updates the address, data and asserts control signals. During this cycle: ? The Master updates the address on the wb_adr_i[7:0] address lines ? Updates the data that will be written to the EFB block, wb_dat_i[7:0] data lines ? Asserts the write enable wb_we_i signal, indicating a write cycle 4

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
? Asserts the wb_cyc_i to indicate the start of the cycle ? Asserts the wb_stb_i, selecting a specific slave module On clock Edge 1, the EFB WISHBONE Slave decodes the input signals presented by the master. During this cycle: ? The Slave decodes the address presented on the wb_adr_i[7:0] address lines ? The Slave prepares to latch the data presented on the wb_dat_i[7:0] data lines ? The Master waits for an active-high level on the wb_ack_o line and prepares to terminate the cycle on the next clock edge, if an active-high level is detected on the wb_ack_o line ? The EFB may insert wait states before asserting wb_ack_o, thereby allowing it to throttle the cycle speed. Any number of wait states may be added ? The Slave asserts wb_ack_o signal The following occurs on clock Edge 2: ? The Slave latches the data presented on the wb_dat_i[7:0] data lines ? The Master de-asserts the strobe signal, wb_stb_i, the cycle signal, wb_cyc_i, and the write enable signal, wb_we_i ? The Slave de-asserts the acknowledge signal, wb_ack_o, in response to the Master de-assertion of the strobe signal Figure 3. WISHBONE Bus Write Operation
Edge 0 Edge 1 Edge 2

wb_clk_i

wb_rst_i

wb_cyc_i

wb_stb_i

wb_we_i VALID ADDRESS

wb_adr_i [7:0]

wb_dat_i [7:0]

VALID DATA

wb_dat_o [7:0]

wb_ack_o

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide WISHBONE Read Cycle
Figure 4 shows the waveform of a Read cycle from the perspective of the EFB WISHBONE Slave interface. During a single Read cycle, only one byte of data is read from the EFB block by the WISHBONE master. A Read operation requires a minimum three clock cycles. On clock Edge 0, the Master updates the address, data and asserts control signals. The following occurs during this cycle: ? The Master updates the address on the wb_adr_i[7:0] address lines ? De-asserts the write enable wb_we_i signal, indicating a Read cycle ? Asserts the wb_cyc_i to indicate the start of the cycle ? Asserts the wb_stb_i, selecting a specific Slave module On clock Edge 1, the EFB WISHBONE slave decodes the input signals presented by the master. The following occurs during this cycle: ? The Slave decodes the address presented on the wb_adr_i[7:0] address lines ? The Master prepares to latch the data presented on wb_dat_o[7:0] data lines from the EFB WISHBONE slave on the following clock edge ? The Master waits for an active-high level on the wb_ack_o line and prepares to terminate the cycle on the next clock edge, if an active-high level is detected on the wb_ack_o line ? The EFB may insert wait states before asserting wb_ack_o, thereby allowing it to throttle the cycle speed. Any number of wait states may be added. ? The Slave presents valid data on the wb_dat_o[7:0] data lines ? The Slave asserts wb_ack_o signal in response to the strobe, wb_stb_i signal

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
The following occurs on clock Edge 2: ? The Master latches the data presented on the wb_dat_o[7:0] data lines ? The Master de-asserts the strobe signal, wb_stb_i, and the cycle signal, wb_cyc_i ? The Slave de-asserts the acknowledge signal, wb_ack_o, in response to the master de-assertion of the strobe signal Figure 4. WISHBONE Bus Read Operation
Edge 0 Edge 1 Edge 2

wb_clk_i

wb_rst_i

wb_cyc_i

wb_stb_i

wb_we_i VALID ADDRESS

wb_adr_i [7:0]

wb_dat_i [7:0] VALID DATA

wb_dat_o [7:0]

wb_ack_o

To avoid simulation mismatch in functional simulations, add a delay of 100ps to wb_cyc_i and wb_stb_i assertion assignments. See the examples below. The examples assume the signal 'wb_cyc_i_gen' is generated elsewhere in the design, for example from a synchronous state machine (SSM). Verilog example: (assumes `timescale 1 ns / 100 ps) assign wb_cyc_i = #0.100 wb_cyc_i_gen; VHDL example: wb_cyc_i <= wb_cyc_i_gen after 100ps; Additionally, ensure your logic monitors for wb_ack_o, and deassert wb_cyc_i and wb_stb_i immediately.

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide WISHBONE Reset Cycle
Figure 5 shows the waveform of the synchronous wb_rst_i signal. Asserting the reset signal will only reset the WISHBONE interface logic. This signal will not affect the contents of any registers in the EFB register map. It will only affect ongoing bus transactions. Figure 5. EFB WISHBONE Interface Reset
Edge 0 Edge 1

wb_clk_i

wb_rst_i

wb_cyc_i

wb_stb_i

The wb_rst_i signal can be asserted for any length of time.

Hardened I2C IP Cores
I2C is a widely used two-wire serial bus for communication between devices on the same board. Every MachXO2 device contains two hardened I2C IP cores designated as the “Primary” and “Secondary” I2C IP cores. Either of the two cores can be operated as an I2C Master or as an I2C Slave. The difference between the two cores is that the Primary core has pre-assigned I/O pins while the ports of the secondary core can be assigned by designers to any general purpose I/O. In addition, the Primary I2C core can be used for accessing the User Flash Memory (UFM) and for programming the Configuration Flash. However, the Primary I2C port cannot be used for both UFM/Config access and user functions in the same design. When instantiating the Hardened I2C IP cores for Slave operations, the EFB 'wb_clk_i' input must be connected to a valid clock source of at least 7.5x the I2C bus rate (for example, >3.0 MHz when I2C rate = 400 kHz).

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

I2C Registers
Both I2C cores communicate with the EFB WISHBONE interface through a set of control, command, status and data registers. Table 3 shows the register names and their functions. These registers are a subset of the EFB register map. Table 3. I2C Registers
I2C Primary Register Name I2C_1_CR I2C_1_CMDR I2C_1_BR0 I2C_1_BR1 I2C_1_TXDR I2C_1_SR I2C_1_GCDR I2C_1_RXDR I2C_1_IRQ I2C_1_IRQEN I2C Secondary Register Name I2C_2_CR I2C_2_CMDR I2C_2_BR0 I2C_2_BR1 I2C_2_TXDR I2C_2_SR I2C_2_GCDR I2C_2_RXDR I2C_2_IRQ I2C_2_IRQEN Register Function Control Command Clock Pre-scale Clock Pre-scale Transmit Data Status General Call Receive Data IRQ IRQ Enable Address I2C Primary 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 Address I2C Secondary 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 Access Read/Write Read/Write Read/Write Read/Write Write Read Read Read Read/Write Read/Write

Note: Unless otherwise specified, all reserved bits in writable registers shall be written ‘0’.

Table 4. I2C Control (Primary/Secondary)
I2C_1_CR / I2C_2_CR Bit Name Default Access 7 I2CEN 0 R/W 6 GCEN 0 R/W 5 WKUPEN 0 R/W 4 (Reserved) 0 — 3 0 R/W 2 0 R/W 1 (Reserved) 0 — 0 — SDA_DEL_SEL[1:0] 0x40/0x4A 0

Note: A write to this register will cause the I2C core to reset.

I2CEN

I2C System Enable Bit – This bit enables the I2C core functions. If I2CEN is cleared, the 2C core is disabled and forced into idle state. 0: I2C function is disabled 1: I2C function is enabled Enable bit for General Call Response – Enables the general call response in slave mode. 0: Disable 1: Enable The General Call address is defined as 0000000 and works with either 7- or 10-bit addressing

GCEN

WKUPEN

Wake-up from Standby/Sleep (by Slave Address matching) Enable Bit – When this bit is enabled the, I2C core can send a wake-up signal to the on-chip power manager to wake the device up from standby/sleep. The wake-up function is activated when the MachXO2 Slave Address is matched during standby/sleep mode. 0: Disable 1: Enable

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
SDA_DEL_SEL[1:0] SDA Output Delay (Tdel) Selection (see Figure 15) 00: 300 ns (min) 300 ns + 2000/[wb_clk_i frequency in MHz] (max) 01: 150 ns (min) 150 ns + 2000/[wb_clk_i frequency in MHz] (max) 10: 75 ns (min) 75 ns + 2000/[wb_clk_i frequency in MHz] (max) 11: 0 ns (min) 0 ns + 2000/[wb_clk_i frequency in MHz] (max)

Table 5. I2C Command (Pri/Sec)
I2C_1_CMDR / I2C_2_CMDR Bit Name Default Access 7 STA 0 R/W 6 STO 0 R/W 5 RD 0 R/W 4 WR 0 R/W 3 ACK 0 R/W 2 CKSDIS 1 R/W 0 — 1 (Reserved) 0 — 0x41/0x4B 0

STA STO RD WR ACK

Generate START (or Repeated START) condition (Master operation) Generate STOP condition (Master operation) Indicate Read from slave (Master operation) Indicate Write to slave (Master operation) Acknowledge Option – when receiving, ACK transmission selection 0: Send ACK 1: Send NACK Clock Stretching Disable. Clock stretching is not supported in this device. Please refer to Lattice Product Change Notice (PCN) #10A-13 for further information. This bit must be set to '1' for all writes to this register.

CKSDIS

Table 6. I2C Clock Prescale 0 (Primary/Secondary)
I2C_1_BR0 / I2C_2_BR0 Bit Name Default1 Access 0 R/W 0 R/W 0 R/W 7 6 5 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W I2C_PRESCALE[7:0] 0 R/W 0x42/0x4C 0

1. Hardware default value may be overridden by EFB component instantiation parameters. See discussion below.

Table 7. I2C Register Clock Prescale 1 (Primary/Secondary)
I2C_1_BR1 / I2C_2_BR1 Bit Name Default1 Access 0 — 0 — 0 — 7 6 5 (Reserved) 0 — 0 — 0 — 4 3 2 1 0 R/W 0x43/0x4D 0 0 R/W I2C_PRESCALE[9:8]

1. Hardware default value may be overridden by EFB component instantiation parameters. See discussion below.

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
I2C_PRESCALE[9:0] I2C Clock Prescale value. A write operation to I2CBR [9:8] will cause an I2C core reset. The WISHBONE clock frequency is divided by (I2C_PRESCALE*4) to produce the Master I2C clock frequency supported by the I2C bus (50 kHz, 100 kHz, 400 kHz).

Note: Different from transmitting a Master, the practical limit for Slave I2C bus speed support is (WISHBONE clock)/2048. For example, the maximum WISHBONE clock frequency to support a 50 kHz Slave I2C operation is 102 MHz. Note: The digital value is calculated by IPexpress? when the I2C core is configured in the I2C tab of the EFB GUI. The calculation is based on the WISHBONE Clock Frequency and the I2C Frequency, both entered by the user. The digital value of the divider is programmed in the MachXO2 device during device programming. After power-up or device reconfiguration, the data is loaded onto the I2C_1_BR1/0 and I2C_2_BR1/0 registers. Registers I2C_1_BR1/0 and I2C_2_BR1/0 have Read/Write access from the WISHBONE interface. Designers can update these clock pre-scale registers dynamically during device operation; however, care must be taken to not violate the I2C bus frequencies. Table 8. I2C Transmit Data Register (Primary/Secondary)
I2C_1_TXDR / I2C_2_TXDR Bit Name Default Access 0 W 0 W 0 W 7 6 5 4 0 W 3 0 W 2 0 W 1 0 W I2C_Transmit_Data[7:0] 0 W 0x44/0x4E 0

I2C_Transmit_Data[7:0]

I2C Transmit Data. This register holds the byte that will be transmitted on the I2C bus during the Write Data phase. Bit 0 is the LSB and will be transmitted last. When transmitting the slave address, Bit 0 represents the Read/Write bit.

Table 9. I2C Status (Primary/Secondary)
I2C_1_SR / I2C_2_SR Bit Name Default Access 7 TIP — R
1

0x45/0x4F 6 BUSY — R
1

5 RARC — R

4 SRW — R

3 ARBL — R

2 TRRDY — R

1 TROE — R

0 HGC — R

1. These bits exhibit 0.5 SCK period latency before valid in R1 devices. For more details on the R1 to Standard migration refer to AN8086, Designing for Migration from MachXO2-1200-R1 to Standard (Non-R1) Devices.

TIP

Transmit In Progress. The current data byte is being transferred. Note that the TIP flag will suffer one-half SCL cycle latency right after the START condition because of the signal synchronization. Also note that this bit could be high after configuration wakeup and before the first valid I2C transfer start (when BUSY is low), and it is not indicating byte in transfer, but an invalid indicator. 1: Byte transfer in progress 0: Byte transfer complete I2C Bus busy. The I2C bus is involved in transaction. This is set at START condition and cleared at STOP. Note only when this bit is set should all other I2C SR bits be treated as valid indicators for a valid transfer. 1: I2C bus busy 0: I2C bus not busy

BUSY

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
RARC Received Acknowledge. An acknowledge response was received by the acknowledge bit monitor. All ACK/NACK bits are monitored and reported, regardless of Master/Slave source or Read/Write mode. 1: No acknowledge received 0: Acknowledge received Slave Read/Write. Indicates transmit or receive mode. 1: Master receiving / slave transmitting 0: Master transmitting / slave receiving Note: SRW is valid after TRRDY=1 following a synchronization delay of up to four WISHBONE clock cycles. Do not test both SRW and TRRDY in the same WISHBONE transaction, but test SRW at least four WISHBONE clock cycles after TRRDY is tested true. This delay is represented in Figure 14. ARBL Arbitration Lost. The core has lost arbitration in Master mode. This bit is capable of generating an interrupt. 1: Arbitration Lost 0: Normal Transmitter or Receiver Ready. The I2C Transmit Data register is ready to receive transmit data, or the I2C Receive Data Register contains receive data (dependent upon master/slave mode and SRW status). This bit is capable of generating an interrupt. 1: 0: TROE Transmitter or Receiver is ready Transmitter of Receiver is not ready

SRW

TRRDY

Transmitter/Receiver Overrun Error. A transmit or receive overrun error has occurred (dependent upon master/slave mode and SRW status). ?

?

Note: When acting as a transmitter (Master Write or Slave Read) a No Acknowledge received will also assert TROE indicating a possible orphan data byte exists in TXDR.? ? This bit is capable of generating an interrupt. 1: Transmitter or Receiver Overrun detected 0: Normal HGC Hardware General Call Received. A hardware general call has been received in slave mode. The corresponding command byte will be available in the General Call Data Register. This bit is capable of generating an interrupt. 1: General Call Received in slave mode 0: Normal

Table 10. I2C General Call Data Register (Primary/Secondary)
I2C_1_GCDR / I2C_2_GCDR Bit Name Default Access — R — R — R 7 6 5 4 — R 3 — R 2 — R 1 — R I2C_GC_Data[7:0] — R 0x46/0x50 0

I2C_ GC _Data[7:0]

I2C General Call Data. This register holds the second (command) byte of the General Call transaction on the I2C bus.

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 11. I2C Receive Data Register (Primary/Secondary)
I2C_1_RXDR / I2C_2_RXDR Bit Name Default Access — R — R — R 7 6 5 4 — R 3 — R 2 — R 1 — R I2C_Receive_Data[7:0] — R 0x47/0x51 0

I2C_ Receive _Data[7:0]

I2C Receive Data. This register holds the byte captured from the I2C bus during the Read Data phase. Bit 0 is LSB and was received last.

Table 12. I2C Interrupt Status (Primary/Secondary)
I2C_1_IRQ / I2C_2_ IRQ Bit Name Default Access — — — — 7 6 (Reserved) — — — — 5 4 3 IRQARBL — R/W 2 IRQTRRDY — R/W 1 IRQTROE — R/W 0x48/0x52 0 IRQHGC — R/W

IRQARBL

Interrupt Status for Arbitration Lost. When enabled, indicates ARBL was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Arbitration Lost Interrupt 0: No interrupt Interrupt Status for Transmitter or Receiver Ready. When enabled, indicates TRRDY was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Transmitter or Receiver Ready Interrupt 0: No interrupt Interrupt Status for Transmitter/Receiver Overrun or NACK received. When enabled, indicates TROE was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Transmitter or Receiver Overrun or NACK received Interrupt 0: No interrupt Interrupt Status for Hardware General Call Received. When enabled, indicates HGC was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: General Call Received in slave mode Interrupt 0: No interrupt

IRQTRRDY

IRQTROE

IRQHGC

Table 13. I2C Interrupt Enable (Primary/Secondary)
I2C_1_ IRQEN / I2C_2_IRQEN Bit Name Default Access 0 — 0 — 7 6 (Reserved) 0 — 0 — 5 4 3 0 R/W 2 0 R/W 1 0 R/W 0x49/0x53 0 0 R/W IRQARBLEN IRQTRRDYEN IRQTROEEN IRQHGCEN

IRQARBLEN

Interrupt Enable for Arbitration Lost 1: Interrupt generation enabled 0: Interrupt generation disabled Interrupt Enable for Transmitter or Receiver Ready 1: Interrupt generation enabled 0: Interrupt generation disabled 13

IRQTRRDYEN

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
IRQTROEEN Interrupt Enable for Transmitter/Receiver Overrun or NACK Received 1: Interrupt generation enabled 0: Interrupt generation disabled Interrupt Enable for Hardware General Call Received 1: Interrupt generation enabled 0: Interrupt generation disabled

IRQHGCEN

Figure 6 shows a flow diagram for controlling Master I2C reads and writes initiated via the WISHBONE interface. The following sequence is for the Primary I2C but the same sequence applies to the Secondary I2C. Figure 6. I2C Master Read/Write Example (via WISHBONE)
Start

TXDR <= I2C addr + ‘W’ CMDR <= 0x94 (STA+WR)

TXDR <= I2C addr + ‘R’ CMDR <= 0x94 (STA+WR)

wait for TRRDY*

wait for SRW

Write more data? Y TXDR <= WRITE_DATA CMDR <=0x14 (WR)

N

CMDR <= 0x24 (RD)

Last Read? N Y

Y

wait **

Read data? N

wait for TRRDY

CMDR <= 0x6C (RD+NACK+STOP)

CMDR <= 0x44 (STOP)

READ_DATA <= RXDR

wait for TRRDY

* Real-Time Write Delay Requirement following TRRDY: 0 < wait < 6*tTCL_period ** Real-Time Read Delay Requirement Read only 1 byte: min < wait < max Read last of 2 bytes: 0 < wait < max where min = 2*tTCL_period max = 7*tTCL_period

READ_DATA <= RXDR

CMDR <=0x04 (CKSDIS)***

*** Optional: Necessary only when External I2C bus masters are present

Done

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Figure 7 shows a flow diagram for reading and writing from an I2C Slave device via the WISHBONE interface. The following sequence is for the Primary I2C but the same sequence applies to the Secondary I2C. Figure 7. I2C Slave Read/Write Example (via WISHBONE)
Start

CMDR <=0x04 (CKSDIS) IRQEN <= 0x00

N wait for not BUSY Write reply data? Y discard <= RXDR discard <= RXDR IRQEN <= 0x04 (TRRDY)*

wait for SRW

Idle

TXDR <= OUT_DATA

wait for TRRDY

Write more data? Y

N

IN_DATA <= RXDR IRQ <= 0x04*

wait for TRRDY

Read more data?

N

TXDR <= OUT_DATA IRQ <= 0x04*

Y * Required only for IRQ driven algorithms

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

Typical I2C Transactions
Figures 8, 9, and 10 illustrate typical User I2C bus protocol transactions that are supported by the Master and Slave flows shown in Figures 6 and 7. Additionally, the figures below reference typical sysConfig Configuration commands structures. Figure 8. Simple I2C Command (for example, ISC_ERASE)
Start Address ACK W CMD ACK OP1 ACK OP2 ACK OP3 ACK Stop

Figure 9. I2C Command with Write Data (for example, LSC_PROG_INCR_NV)
Start Address ACK W CMD ACK OP1 ACK OP2 ACK OP3 ACK Stop WDATAn ACK

WDATA1 ACK

WDATA2 ACK


OP2 ACK ACK ACK

Figure 10. I2C Command with Read Data (for example, LSC_READ_STATUS)
Start Address ACK Restart Address ACK R RDATA1 W CMD ACK ACK RDATA2 OP1 OP3 ACK NACKStop RDATAn



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Figure 11. EFB Master – I2C Write
Master Stop 9 Idle AD6 Ack from Slave D[7:0] D[7:0] Ack from Slave AD5 AD4 AD3 AD0 Write D7 D6 D5 D1 D0 D7 D6 D5 AD2 AD1 D4 D3 D2 D4 D3 D2 D1 D0 Ack from Slave

I2C Functional Waveforms

1 9 1

9

1

SCL

Master Start

SDA

I2C_1_TXDR

AD[(6:0),W]

I2C_1_CMDR 0x14(WR)

0x94(Start+WR)

0x14(WR)

0x44(STOP)

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

17
Write I2C_1_TXDR Write I2C_1_TXDR Write IRQTRRDY Write IRQTRRDY

I2C_1_SR[BUSY]

I2C_1_SR[SRW]

I2C_1_SR[TRRDY] Write IRQTRRDY

I2C_1_IRQ[IRQTRRDY]

I2C_1_SR[RARC]

Figure 12. EFB Master – I2C Read

1

9

1

9

1

9

SCL

SDA AD6 Ack from Slave Ack from Master AD5 AD4 AD0 Read D7 D6 D5 D1 D0 D7 D6 D5

AD3

AD2

AD1

D4

D3

D2

D4

D3

D2

D1

D0 Nack from Master Stop from Master

Master Start/ Restart

I2C_1_TXDR

AD[(6:0),W]

I2C_1_RXDR

D[7:0]

D[7:0]

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

18
0x24 (RD) Write IRQTRRDY

I2C_1_CMDR

0x94 (START+WR)

0x6C (RD+NACK+STOP)

I2C_1_SR[BUSY]

I2C_1_SR[SRW] Read I2C1_RXDR Read I2C1_RXDR

I2C_1_SR[TRRDY] Write IRQTRRDY Write IRQTRRDY

I2C_1_IRQ[IRQTRRDY]

Figure 13. EFB Slave – I2C Write

1

9

1

9

1

9

SCL

SDA AD4 Ack from Slave Ack from Slave AD0 Write D7 D6 D5 D1 D0 D7 D6 D5

AD6

AD5

AD3

AD2

AD1

D4

D3

D2

D4

D3

D2

D1

D0 Ack from Slave Stop from Master

Start from Master

I2C_1_TXDR

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

19
D[7:0]

I2C_1_RXDR

D[7:0]

I2C_1_SR[BUSY]

I2C_1_SR[SRW] Read I2C_1_RXDR Read I2C_1_RXDR

I2C_1_SR[TRRDY] Write IRQTRRDY Write IRQTRRDY

I2C_1_IRQ[IRQTRRDY]

Figure 14. EFB Slave – I2C Read

1

9

1

9 1

9

SCL

SDA AD5 Ack from Slave D[7:0] D[7:0] Ack from Master AD4 AD0 Read D7 D6 D5 D1 D0 D7 D6 D5

AD6

AD3

AD2

AD1

D4

D3

D2

D4

D3

D2

D1

D0 No Ack from Master Stop from Master

Start from Master

I2C_1_TXDR

I2C_1_RXDR

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

20
Write I2C_1_TXDR Write I2C_1_TXDR Write IRQTRRDY Write IRQTRRDY Write IRQTRRDY

I2C_1_SR[BUSY]

I2C_1_SR[SRW]

I2C_1_SR[TRRDY]

I2C_1_IRQ[IRQTRRDY]

I2C_1_SR[RARC]

Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

I2C Timing Diagram
Figure 15. I2C Bit Transfer Timing
tSDA_DEL

SCL

SDA

data line stable; data valid

change of data allowed

I2C Simulation Model
The I2C EFB Register Map translation to the MachXO2 EFB software simulation model is provided in below. Table 14. I2C Primary Simulation Mode
I2C Primary Register Name I2C_1_CR I2CEN GCEN WKUPEN SDA_DEL_SEL[1:0] I2C_1_CMDR STA STO RD WR ACK CKSDIS I2C_1_BR0 I2C_PRESCALE[7:0] I2C_1_BR1 I2C_PRESCALE[9:8] I2C_1_TXDR I2C_Transmit_Data[7:0] I2C_1_SR Register Size/Bit Location [7:0] 7 6 5 [3:2] [7:0] 7 6 5 4 3 2 [7:0] [7:0] [7:0] [1:0] [7:0] [7:0] [7:0] Status 0x45 Read Transmit Data 0x44 Write Clock Pre-scale 0x43 Clock Pre-scale 0x42 Command 0x41 Register Function Control Address I2C Primary 0x40 Access Simulation Model Register Name Simulation Model Register Path ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/

Read/Write i2ccr1[7:0] i2c_en i2c_gcen i2c_wkupen sda_del_sel Read/Write i2ccmdr[7:0] i2c_sta i2c_sto i2c_rd i2c_wt i2c_nack i2c_cksdis Read/Write i2cbr[7:0] i2cbr[7:0] Read/Write i2cbr[9:8] i2cbr[9:8] i2ctxdr[7:0] i2ctxdr[7:0] i2csr[7:0]

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 14. I2C Primary Simulation Mode (Continued)
I2C Primary Register Name TIP BUSY RARC SRW ARBL TRRDY TROE HGC I2C_1_GCDR I2C_GC_Data[7:0] I2C_1_RXDR I2C_Receive_Data[7:0] Register Size/Bit Location 7 6 5 4 3 2 1 0 [7:0] [7:0] [7:0] [7:0] Receive Data 0x47 Read General Call 0x46 Read Register Function Address I2C Primary Access Simulation Model Register Name i2c_tip_sync i2c_busy_sync i2c_rarc_sync i2c_srw_sync i2c_arbl i2c_trrdy i2c_troe i2c_hgc i2cgcdr[7:0] i2cgcdr[7:0] i2crxdr[7:0] i2crxdr[7:0] {1'b0, 1'b0, 1'b0, 1'b0, i2csr_1st_irqsts_3, Read/Write i2csr_1st_irqsts_2, i2csr_1st_irqsts_1, i2csr_1st_irqsts_0} i2csr_1st_irqsts_3 i2csr_1st_irqsts_2 i2csr_1st_irqsts_1 i2csr_1st_irqsts_0 {1'b0, 1'b0, 1'b0, 1'b0, i2csr_1st_irqena_3, Read/Write i2csr_1st_irqena_2, i2csr_1st_irqena_1, i2csr_1st_irqena_0} i2csr_1st_irqena_3 i2csr_1st_irqena_2 i2csr_1st_irqena_1 i2csr_1st_irqena_0 Simulation Model Register Path ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_1st/

I2C_1_IRQ

[7:0]

IRQ

0x48

../efb_top/efb_pll_sci_inst/u_efb_sci/

IRQARBL IRQTRRDY IRQTROE IRQHGC

3 2 1 0

../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/

I2C_1_IRQEN

[7:0]

IRQ Enable

0x49

../efb_top/efb_pll_sci_inst/u_efb_sci/

IRQARBLEN IRQTRRDYEN IRQTROEEN IRQHGCEN

3 2 1 0

../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 15. I2C Secondary Simulation Model
I2C Secondary Register Name I2C_2_CR I2CEN GCEN WKUPEN SDA_DEL_SEL[1:0] I2C_2_CMDR STA STO RD WR ACK CKSDIS I2C_2_BR0 I2C_PRESCALE[7:0] I2C_2_BR1 I2C_PRESCALE[9:8] I2C_2_TXDR I2C_Transmit_Data[7:0] I2C_2_SR TIP BUSY RARC SRW ARBL TRRDY TROE HGC I2C_2_GCDR I2C_GC_Data[7:0] I2C_2_RXDR I2C_Receive_Data[7:0] Register Size/Bit Location [7:0] 7 6 5 [3:2] [7:0] 7 6 5 4 3 2 [7:0] [7:0] [7:0] [1:0] [7:0] [7:0] [7:0] 7 6 5 4 3 2 1 0 [7:0] [7:0] [7:0] [7:0] Receive Data 0x51 Read General Call 0x50 Read Status 0x4F Read Transmit Data 0x4E Write Clock Pre-scale 0x4D Clock Pre-scale 0x4C Command 0x4B Register Function Control Address I2C Secondary 0x4A Access Simulation Model Register Name Simulation Model Register Path ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/i2c_2nd/

Read/Write i2ccr1[7:0] i2c_en i2c_gcen i2c_wkupen sda_del_sel Read/Write i2ccmdr[7:0] i2c_sta i2c_sto i2c_rd i2c_wt i2c_nack i2c_cksdis Read/Write i2cbr[7:0] i2cbr[7:0] Read/Write i2cbr[9:8] i2cbr[9:8] i2ctxdr[7:0] i2ctxdr[7:0] i2csr[7:0] i2c_tip_sync i2c_busy_sync i2c_rarc_sync i2c_srw_sync i2c_arbl i2c_trrdy i2c_troe i2c_hgc i2cgcdr[7:0] i2cgcdr[7:0] i2crxdr[7:0] i2crxdr[7:0]

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 15. I2C Secondary Simulation Model (Continued)
I2C Secondary Register Name Register Size/Bit Location Register Function Address I2C Secondary Access Simulation Model Register Name Simulation Model Register Path

I2C_2_IRQ

[7:0]

IRQ

0x52

{1'b0, 1'b0, 1'b0, 1'b0, i2csr_2nd_irqsts_3, Read/Write i2csr_2nd_irqsts_2, i2csr_2nd_irqsts_1, i2csr_2nd_irqsts_0} i2csr_2nd_irqsts_3 i2csr_2nd_irqsts_2 i2csr_2nd_irqsts_1 i2csr_2nd_irqsts_0 {1'b0, 1'b0, 1'b0, 1'b0, i2csr_2nd_irqena_3, Read/Write i2csr_2nd_irqena_2, i2csr_2nd_irqena_1, i2csr_2nd_irqena_0} i2csr_2nd_irqena_3 i2csr_2nd_irqena_2 i2csr_2nd_irqena_1 i2csr_2nd_irqena_0

../efb_top/efb_pll_sci_inst/u_efb_sci/

IRQARBL IRQTRRDY IRQTROE IRQHGC

3 2 1 0

../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/

I2C_2_IRQEN

[7:0]

IRQ Enable

0x53

../efb_top/efb_pll_sci_inst/u_efb_sci/

IRQARBLEN IRQTRRDYEN IRQTROEEN IRQHGCEN

3 2 1 0

../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/

Hardened SPI IP Core
The MachXO2 EFB contains a hard SPI IP core that can be configured as a SPI Master or Slave. When the SPI core is configured as a Master it is able to control other devices with Slave SPI interfaces that are connected to the SPI bus. When the SPI core is configured as a Slave, it is able to interface to an external SPI Master device.

SPI Registers
The SPI core communicates with the WISHBONE interface through a set of control, command, status and data registers. Table 16 shows the register names and their functions. These registers are a subset of the EFB register map. Table 16. SPI Registers
SPI Register Name SPICR0 SPICR1 SPICR2 SPIBR SPICSR SPITXDR SPISR SPIRXDR SPIIRQ SPIIRQEN Register Function Control Register 0 Control Register 1 Control Register 2 Clock Pre-scale Master Chip Select Transmit Data Status Receive Data Interrupt Request Interrupt Request Enable Address 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D Access Read/Write Read/Write Read/Write Read/Write Read/Write Write Read Read Read/Write Read/Write

Note: Unless otherwise specified, all Reserved bits in writable registers shall be written ‘0’.

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 17. SPI Control 0
SPICR0 Bit Name Default Access 7 0 R/W 6 0 R/W 5 0 R/W 4 TTrail_XCNT[2:0] 0 R/W 0 R/W 0 R/W 3 2 1 TLead_XCNT[2:0] 0 R/W 0 R/W 0 TIdle_XCNT[1:0] 0x54

Note: A write to this register will cause the SPI core to reset.

TIdle_XCNT[1:0]

Idle Delay Count. Specifies the minimum interval prior to the Master Chip Select low assertion (Master Mode only), in SCK periods. 00: ? 01: 1 10: 1.5 11: 2 Trail Delay Count. Specifies the minimum interval between the last edge of SCK and the high deassertion of Master Chip Select (Master Mode only), in SCK periods. 000: ? 001: 1 010: 1.5 … 111: 4 Lead Delay Count. Specifies the minimum interval between the Master Chip Select low assertion and the first edge of SCK (Master Mode only), in SCK periods. 000: ? 001: 1 010: 1.5 … 111: 4

TTrail_XCNT[2:0]

TLead_XCNT[2:0]

Table 18. SPI Control 1
SPICR1 Bit Name Default Access 7 SPE 0 R/W 6 0 R/W 5 0 R/W 4 TXEDGE 0 R/W 0 — 0 — 3 2 (Reserved) 0 — 0 — 1 0 WKUPEN_USER WKUPEN_CFG 0x55

Note: A write to this register will cause the SPI core to reset.

SPE

This bit enables the SPI core functions. If SPE is cleared, SPI is disabled and forced into idle state. 0: SPI disabled 1: SPI enabled, port pins are dedicated to SPI functions. Wake-up Enable via User. Enables the SPI core to send a wake-up signal to the onchip Power Controller to wake the part from Standby mode when the User slave SPI chip select (spi_scsn) is driven low. 0: Wakeup disabled 1: Wakeup enabled.

WKUPEN_USER

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
WKUPEN_CFG Wake-up Enable Configuration. Enables the SPI core to send a wake-up signal to the on-chip power controller to wake the part from standby mode when the Configuration slave SPI chip select (ufm_sn) is driven low. 0: Wakeup disabled 1: Wakeup enabled. Data Transmit Edge. Enables Lattice proprietary extension to the SPI protocol. Selects which clock edge to transmit SPI data. Refer to Figure 24 through Figure 27. 0: 1: Table 19. SPI Control 2
SPICR2 Bit Name Default Access 7 MSTR 0 R/W 6 MCSH 0 R/W 5 SDBRE 0 R/W 4 (Reserved) 0 — 3 (Reserved) 0 — 2 CPOL 0 R/W 1 CPHA 0 R/W 0 LSBF 0 R/W 0x56

TXEDGE

Transmit data on the MCLK/CCLK edge defined by SPICR2[CPOL] and SPICR2[CPHA] Transmit data ? MCLK/CCLK edge earlier than defined by SPICR2[CPOL] and SPICR2[CPHA]

Note: A write to this register will cause the SPI core to reset.

MSTR

SPI Master/Slave Mode. Selects the Master/Slave operation mode of the SPI core. Changing this bit forces the SPI system into idle state. 0: SPI is in Slave mode 1: SPI is in Master mode SPI Master CSSPIN Hold. Holds the Master chip select active when the host is busy, to halt the data transmission without de-asserting chip select. Note: This mode must be used only when the WISHBONE clock has been divided by a value greater than four (4) (greater than six (6) for R1 devices). For more details on the R1 to Standard migration refer to AN8086, Designing for Migration from MachXO2-1200-R1 to Standard (Non-R1) Devices. 0: Master running as normal 1: Master holds chip select low even if there is no data to be transmitted

MCSH

SDBRE

Slave Dummy Byte Response Enable. Enables Lattice proprietary extension to the SPI protocol. For use when the internal support circuit (for example, WISHBONE host) cannot respond with initial data within the time required, and to make the slave read out data predictably available at high SPI clock rates. When enabled, dummy 0xFF bytes will be transmitted in response to a SPI slave read (while SPISR[TRDY]=1) until an initial write to SPITXDR. Once a byte is written into SPITXDR by the WISHBONE host, a single byte of 0x00 will be transmitted then followed immediately by the data in SPITXDR. In this mode, the external SPI master should scan for the initial 0x00 byte when reading the SPI slave to indicate the beginning of actual data. Refer to Figure 23. 0: Normal Slave SPI operation 1: Lattice proprietary Slave Dummy Byte Response Enabled Note: This mechanism only applies for the initial data delay period. Once the initial data is available, subsequent data must be supplied to SPITXDR at the required SPI bus data rate.

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
CPOL SPI Clock Polarity. Selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical SPICR2[CPOL] values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. Refer to Figure 24 through Figure 27. 0: Active-high clocks selected. 1: Active-low clocks selected. SPI Clock Phase. Selects the SPI clock format. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. Refer to Refer to Figure 24 through Figure 27. 0: Data is captured on a leading (first) clock edge, and propagated on the opposite clock edge. 1: Data is captured on a trailing (second) clock edge, and propagated on the opposite clock edge*. Note: When CPHA=1, the user must explicitly place a pull-up or pull-down on SCK pad corresponding to the value of CPOL (for example, when CPHA=1 and CPOL=0 place a pull-down on SCK). When CPHA=0, the pull direction may be set arbitrarily. Slave SPI Configuration mode supports default setting only for CPOL, CPHA. LSBF LSB-First. LSB appears first on the SPI interface. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. Refer to Figure 24 through Figure 27. Note: This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in bit 7. 0: Data is transferred most significant bit (MSB) first 1: Data is transferred least significant bit (LSB) first Table 20. SPI Clock Prescale
SPIBR Bit Name Default1 Access 0 — 7 (Reserved) 0 — 0 R/W 0 R/W 6 5 4 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W DIVIDER[5:0] 0x57

CPHA

1. Hardware default value may be overridden by EFB component instantiation parameters. See discussion below.

DIVIDER[5:0]

SPI Clock Prescale value. The WISHBONE clock frequency is divided by (DIVIDER[5:0] + 1) to produce the desired SPI clock frequency. A write operation to this register will cause a SPI core reset. DIVIDER must be >= 1. Note: The digital value is calculated by IPexpress when the SPI core is configured in the SPI tab of the EFB GUI. The calculation is based on the WISHBONE Clock Frequency and the SPI Frequency, both entered by the user. The digital value of the divider is programmed in the MachXO2 device during device programming. After power-up or device reconfiguration, the data is loaded onto the SPIBR register. Register SPIBR has Read/Write access from the WISHBONE interface. Designers can update the clock pre-scale register dynamically during device operation.

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 21. SPI Master Chip Select
SPICSR Bit Name Default Access 7 CSN_7 0 R/W 6 CSN_6 0 R/W 5 CSN_5 0 R/W 4 CSN_4 0 R/W 3 CSN_3 0 R/W 2 CSN_2 0 R/W 1 CSN_1 0 R/W 0 CSN_0 0 R/W 0x58

CSN_[7:0]

SPI Master Chip Selects. Used in master mode for asserting a specific Master Chip Select (MCSN) line. The register has eight bits, enabling the SPI core to control up to eight external SPI slave devices Each bit represents one master chip select line (Active-Low). Bits [7:1] may be connected to any I/O pin via the FPGA fabric. Bit 0 has a pre-assigned pin location. The register has Read/Write access from the WISHBONE interface. A write operation on this register will cause the SPI core to reset.

Table 22. SPI Transmit Data Register
SPITXDR Bit Name Default Access — W — W — W 7 6 5 4 — W 3 — W 2 — W 1 — W 0 — W SPI_Transmit_Data[7:0] 0x59

SPI_Transmit_Data[7:0]

SPI Transmit Data. This register holds the byte that will be transmitted on the SPI bus. Bit 0 in this register is LSB, and will be transmitted last when SPICR2[LSBF]=0 or first when SPICR2[LSBF]=1. Note: When operating as a Slave, SPITXDR must be written when SPISR[TRDY] is '1' and at least 0.5 CCLKs before the first bit is to appear on SO. For example, when CPOL = CPHA = TXEDGE = LSBF = 0, SPITXDR must be written prior to the CCLK rising edge used to sample the LSB (bit 0) of the previous byte. See Figure 29. This timing requires at least one protocol dummy byte be included for all slave SPI read operations.

Table 23. SPI Status
SPISR Bit Name Default Access 7 TIP 0 R — — 6 (Reserved) — — 5 4 TRDY 0 R 3 RRDY 0 R 2 (Reserved) — — 1 ROE 0 R 0 MDF 0 R 0x5A

TIP

SPI Transmitting In Progress. Indicates the SPI port is actively transmitting/receiving data. 0: SPI Transmitting complete 1: SPI Transmitting in progress* Note: This bit is non-functional in R1 devices. For more details on the R1 to Standard migration refer to AN8086, Designing for Migration from MachXO2-1200-R1 to Standard (Non-R1) Devices.

TRDY

SPI Transmit Ready. Indicates the SPI transmit data register (SPITXDR) is empty. This bit is cleared by a write to SPITXDR. This bit is capable of generating an interrupt. 0: SPITXDR is not empty 1: SPITXDR is empty

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
RRDY SPI Receive Ready. Indicates the receive data register (SPIRXDR) contains valid receive data. This bit is cleared by a read access to SPIRXDR. This bit is capable of generating an interrupt. 0: SPIRXDR does not contain data 1: SPIRXDR contains valid receive data Receive Overrun Error. Indicates SPIRXDR received new data before the previous data was read. The previous data is lost. This bit is capable of generating an interrupt. 0: Normal 1: Receiver Overrun detected Mode Fault. Indicates the Slave SPI chip select (spi_scsn) was driven low while SPICR2[MSTR]=1. This bit is cleared by any write to SPICR0, SPICR1 or SPICR2. This bit is capable of generating an interrupt. 0: Normal 1: Mode Fault detected

ROE

MDF

Table 24. SPI Receive Data Register
SPIRXDR Bit Name Default Access 0 R 0 R 0 R 7 6 5 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R SPI_Receive_Data[7:0] 0x5B

SPI_Receive_Data[7:0]

SPI Receive Data. This register holds the byte captured from the SPI bus. Bit 0 in this register is LSB and was received last when LSBF=0 or first when LSBF=1.

Table 25. SPI Interrupt Status
SPIIRQ Bit Name Default Access — — 7 6 (Reserved) — — — — 5 4 IRQTRDY 0 R/W 3 IRQRRDY 0 R/W 2 (Reserved) — — 1 IRQROE 0 R/W 0 IRQMDF 0 R/W 0x5C

IRQTRDY

Interrupt Status for SPI Transmit Ready. When enabled, indicates SPISR[TRDY] was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: SPI Transmit Ready Interrupt 0: No interrupt Interrupt Status for SPI Receive Ready. When enabled, indicates SPISR[RRDY] was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: SPI Receive Ready Interrupt 0: No interrupt Interrupt Status for Receive Overrun Error. When enabled, indicates ROE was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Receive Overrun Error Interrupt 0: No interrupt?

IRQRRDY

IRQROE

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
IRQMDF Interrupt Status for Mode Fault. When enabled, indicates MDF was asserted. Write a ‘1’ to this bit to clear the interrupt. 1: Mode Fault Interrupt 0: No interrupt

Table 26. SPI Interrupt Enable
SPIIRQEN Bit Name Default Access 0 — 7 6 (Reserved) 0 — 0 — 5 4 0 R/W 3 0 R/W 2 0 — 1 0 R/W 0 0 R/W IRQTRDYEN IRQRRDYEN (Reserved) 0x5D IRQROEEN IRQMDFEN

IRQTRDYEN

Interrupt Enable for SPI Transmit Ready. 1: Interrupt generation enabled 0: Interrupt generation disabled Interrupt Enable for SPI Receive Ready 1: Interrupt generation enabled 0: Interrupt generation disabled Interrupt Enable for Receive Overrun Error 1: Interrupt generation enabled 0: Interrupt generation disabled Interrupt Enable for Mode Fault 1: Interrupt generation enabled 0: Interrupt generation disabled

IRQRRDYEN

IRQROEEN

IRQMDFEN

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Figure 16 shows a flow diagram for controlling Master SPI reads and writes initiated via the WISHBONE interface. Figure 16. SPI Master Read/Write Example (via WISHBONE) – Production Silicon
Start

CR2 <= 0xC0

wait for TRDY

Read data? N

Y

TXDR <= SPI Write Data

TXDR <= 0x00

wait for RRDY

wait for RRDY

Discard Data <= RXDR

SPI Read Data <= RXDR

N

Done? Y

Last Read? Y

N

CR2 <= 0x80

wait for not TIP

Done

Note: Assumes CR2 register, MSCH = '1'. The algorithm when MSCH = '0' is application dependent and not provided. See Figure 22 for guidance.

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Figure 17. SPI Master Read/Write Example (via WISHBONE) – R1 Silicon
Start

CR2 <= 0xC0

wait for TRDY

TXDR <= 0x00

TXDR <= SPI Command Byte

wait for RRDY

Y

Done? N Y

Discard Data <= RXDR

Read data? N

TXDR <= 0x00

TXDR <= SPI Write Data

wait for RRDY

wait for RRDY

SPI Read Data <= RXDR

Discard Data <= RXDR

Last Read? Y

N

CR2 <= 0x80

Done

Note: For more details on the R1 to Standard migration refer to AN8086, Designing for Migration from MachXO21200-R1 to Standard (Non-R1) Devices.

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Figure 18. SPI Slave Read/Write Example (via WISHBONE) - Production Silicon

Start

CR2 <=0x00 (Slave mode)

wait for not TIP

discard <= RXDR discard <= RXDR TXDR <= T1 data (optional)*

Idle

Write reply data? N Y

wait for TIP

wait for TRDY

TXDR <= T2 data (dum1)*

TXDR <= Tn+1 data

wait for RRDY

Read more data? N Y

R1 data <= RXDR

wait for RRDY

wait for TRDY

Rn data <= RXDR

TXDR <= T3 data

Transaction Complete? N

Y

wait for RRDY

R2 data <= RXDR

* If T1 data is not written, then T2 data is dummy and 0xFF will be transmitted on SO.

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

Typical SPI Transactions
Figures 19, 20, and 21 illustrate typical User SPI bus protocol transactions that are supported by the Master and Slave flows shown in Figures 16, 17, and 18. Additionally, the figures below reference typical sysConfig Configuration commands structures. Figure 19. Simple SPI Command (for example, ISC_ERASE)
MOSI MISO CSN CMD OP1 OP2 OP3 -

Figure 20. SPI Command w/ Write Data (for example, LSC_PROG_INCR_NV)
MOSI MISO CSN CMD OP1 OP2 OP3 WDATA1 WDATA2 ... ... WDATAn -

Figure 21. SPI Command w/ Read Data (for example, LSC_READ_STATUS)
MOSI MISO CSN CMD OP1 OP2 OP3 RDATA1 RDATA2 ... ... RDATAn

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

SPI Functional Waveforms
Figure 22. Fully Specified SPI Transaction (MachXO2 as SPI Master or Slave)
R1 from SI to SPIRXDR (auto) R1 read from SPIRXDR via WISHBONE (user)

SPISR[RRDY] SPIRXDR R1 R2 R3 R4 R5 R6 R7 R8

SPISR[TIP]

SPISO or SI

R1

R2

R3

R4

R5

R6

R7

R8

SISPI or SO

T1

T2

T3

T4

T5

T6

T7

T8

CSSPIN or SCSN

SPITXDR SPISR[TRDY]

T1

T2

T3

T4

T5

T6

T7

T8

T1 written to SPITXDR via WISHBONE (user)

T1 from SPITXDR to SO (auto)

Figure 23. Minimally Specified SPI Transaction Example (MachXO2 as SPI Slave)
CMD read from SPIRXDR via WISHBONE (user)
SPISR[RRDY] SPISR[ROE] SPIRXDR

Addr read from SPIRXDR via WISHBONE (user) Quit reading SPIRXDR (data is “don’t care”)

Flush SPIRXDR via WISHBONE (user)

0x08

addr

dum

SPISR[TIP]

SI

0x08

addr Command

dum Reply to Command dum2 D1 D2 D3 D4 D5

SO

old

FF*

SCSN

SPITXDR SPISR[TRDY]

old

dum1

dum2

D1

D2

D3

D4

D5

After SPISR[TIP] detected, write dummy to SPITXDR (user)

After CMD/Addr decode, write good to SPITXDR (user)

*Note: If SPITXDR is ‘empty’ at the start of a transaction, the second byte will be ‘FF’ (silicon limitation). Must write dummy byte in first byte period to get good Tx data in third period (dummy data may be overwritten in second period if necessary).

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

SPI Timing Diagrams
Figure 24. SPI Control Timing (SPICR2[CPHA]=0, SPICR1[TXEDGE]=0)
Signal Name: MASTER/SLAVE MCLK/CCLK (CPOL=0) MCLK/CCLK (CPOL=1) SPISO/SI SISPI/SO CSSPIN/SCSN or SN sample instants

tL MSB first (LSBF=0): LSB first (LSBF=1): tL = TLead_XCNT tT = TTrail_XCNT tL = TIdle_XCNT MSB LSB bit6 bit1 bit5 bit2 bit4 bit3 bit3 bit4 bit2 bit5 bit1 bit6 LSB MSB

tT

tI

tL

*Note: MachXO2 SPI configuration modes only support CPHA = CPOL = LSBF = TXEDGE = 0

Figure 25. SPI Control Timing (SPICR2[CPHA]=1, SPICR1[TXEDGE]=0)
Signal Name: MASTER/SLAVE

sample instants

MCLK/CCLK (CPOL=0) MCLK/CCLK (CPOL=1) SPISO/SI SISPI/SO CSSPIN/SCSN

tL MSB first (LSBF=0): LSB first (LSBF=1): tL = TLead_XCNT tT = TTrail_XCNT tL = TIdle_XCNT MSB LSB bit6 bit1 bit5 bit2 bit4 bit3 bit3 bit4 bit2 bit5 bit1 bit6 LSB

tT

tI

tL

MSB

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Figure 26. SPI Control Timing (SPICR2[CPHA]=0, SPICR1[TXEDGE]=1)
Signal Name: MASTER/SLAVE MCLK/CCLK (CPOL=0) MCLK/CCLK (CPOL=1) SPISO/SI SISPI/SO

sample instants

CSSPIN/SCSN

tL MSB first (LSBF=0): LSB first (LSBF=1): tL = TLead_XCNT tT = TTrail_XCNT tL = TIdle_XCNT MSB LSB bit6 bit1 bit5 bit2 bit4 bit3 bit3 bit4 bit2 bit5 bit1 bit6 LSB MSB

tT

tI

tL

Figure 27. SPI Control Timing (SPICR2[CPHA]=1, SPICR1[TXEDGE]=1)
Signal Name: MASTER/SLAVE

sample instants

MCLK/CCLK (CPOL=0) MCLK/CCLK (CPOL=1) SPISO/SI SISPI/SO CSSPIN/SCSN

tL MSB first (LSBF=0): LSB first (LSBF=1): tL = TLead_XCNT tT = TTrail_XCNT tL = TIdle_XCNT MSB LSB bit6 bit1 bit5 bit2 bit4 bit3 bit3 bit4 bit2 bit5 bit1 bit6 LSB

tT

tI

tL

MSB

Figure 28. Slave SPI Dummy Byte Response (SPICR2[SDBRE]) Timing
SI(MOSI) CS(SS) SO(MISO) FF FF FF FF FF SPITXDR NOT Ready FF 00 D1 D2 D3 CMD OP1 OP2 OP3 FF FF FF FF FF FF

Receiving Read Command

SPITXDR Ready

DATA Read Out

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

SPI Simulation Model
The SPI EFB Register Map translation to the MachXO2 EFB software simulation model is provided below. Table 27. SPI Simulation Model
SPI Register Name SPICR0 TIdle_XCNT[1:0] TTrail_XCNT[2:0] TLead_XCNT[2:0] SPICR1 SPE WKUPEN_USER WKUPEN_CFG TXEDGE SPICR2 MSTR MCSH SDBRE CPOL CPHA LSBF SPIBR DIVIDER[5:0] SPICSR CSN_7 CSN_6 CSN_5 CSN_4 CSN_3 CSN_2 CSN_1 CSN_0 SPITXDR SPI_Transmit_Data[7:0] Register Size/Bit Location [7:0] [7:6] [5:3] [2:0] [7:0] 7 6 5 4 [7:0] 7 6 5 2 1 0 [7:0] [5:0] [7:0] 7 6 5 4 3 2 1 0 [7:0] [7:0] Transmit Data 0x59 Write Master Chip Select 0x58 Clock Pre-scale 0x57 Control Register 2 0x56 Control Register 1 0x55 Register Function Control Register 0 Address 0x54 Access Simulation Model Register Name Simulation Model Register Path ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/

Read/Write spicr0[7:0] spicr0[7:6] spicr0[5:3] spicr0[2:0] Read/Write spicr1[7:0] spi_en spi_wkup_usr spi_wkup_cfg spi_tx_edge Read/Write spicr2[7:0] spi_mstr spi_mcsh spi_srme spi_cpol spi_cpha spi_lsbf Read/Write spibr[7:0] spibr[5:0] Read/Write spicsr[7:0] spicsr[7] spicsr[6] spicsr[5] spicsr[4] spicsr[3] spicsr[2] spicsr[1] spicsr[0] spitxdr[7:0] spitxdr[7:0]

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Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide
Table 27. SPI Simulation Model (Continued)
SPI Register Name SPISR TIP TRDY RRDY ROE MDF SPIRXDR SPI_Receive_Data[7:0] Register Size/Bit Location [7:0] 7 4 3 1 0 [7:0] [7:0] Receive Data 0x5B Read Register Function Status Address 0x5A Access Read Simulation Model Register Name spisr[7:0] spi_tip_sync spi_trdy spi_rrdy spi_roe spi_mdf spirxdr[7:0] spirxdr[7:0] {1'b0, 1'b0, 1'b0, spisr_irqsts_4, Read/Write spisr_irqsts_3, spisr_irqsts_2, spisr_irqsts_1, spisr_irqsts_0} spisr_irqsts_4 spisr_irqsts_3 spisr_irqsts_1 spisr_irqsts_0 {1'b0, 1'b0, 1'b0, spisr_irqena_4, spisr_irqena_3, Read/Write spisr_irqena_2, spisr_irqena_1, spisr_irqena_0} spisr_irqena_4 spisr_irqena_3 spisr_irqena_1 spisr_irqena_0 Simulation Model Register Path ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/ ../efb_top/config_plus_inst/config_core_inst/cfg_cdu/ njport_unit/spi_port/

SPIIRQ

[7:0]

Interrupt Request

0x5C

../efb_top/efb_pll_sci_inst/u_efb_sci/

IRQTRDY IRQRRDY IRQROE IRQMDF

4 3 1 0

../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/

SPIIRQEN

[7:0]

Interrupt Request Enable

0x5D

../efb_top/efb_pll_sci_inst/u_efb_sci/

IRQTRDYEN IRQRRDYEN IRQROEEN IRQMDFEN

4 3 1 0

../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/ ../efb_top/efb_pll_sci_inst/u_efb_sci/

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