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V-by-One HS Standard_Ver.1.4

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Abridged Edition

V-by-One? HS Standard Version 1.4
December 15, 2011

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V-by-One HS Standard_Ver.1.4

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Abridged Edition
Table of Contents

Table of Contents................................................................................................................................................. 2 1. Introduction ..................................................................................................................................................... 4 1.1. 1.2. Objectives................................................................................................................................................ 4 Technical Overview................................................................................................................................. 4 Transmitter....................................................................................................................................... 5 Receiver........................................................................................................................................... 5 Data Lane ........................................................................................................................................ 5 HTPDN signal ................................................................................................................................. 7 LOCKN signal................................................................................................................................. 7

1.2.1. 1.2.2. 1.2.3. 1.2.4. 1.2.5. 2. 2.1.

Link Specification ........................................................................................................................................... 8 Functional Specification.......................................................................................................................... 9 Packer and Unpacker....................................................................................................................... 9 Scrambler and Descrambler........................................................................................................... 14 Encoder and Decoder .................................................................................................................... 17 Serializer and Deserializer............................................................................................................. 18 Link status monitor........................................................................................................................ 19 Transmitter State Diagram............................................................................................................. 20 Receiver State Diagram ................................................................................................................. 21 Link Start up flow.......................................................................................................................... 22 Link Disable flow .......................................................................................................................... 23 Trainings........................................................................................................................................ 24 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5.

Operating Specification ......................................................................................................................... 20

3.

Electrical Specification.................................................................................................................................. 28 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. Overview ............................................................................................................................................... 28 Transmitter Electrical Specifications..................................................................................................... 29 Receiver Electrical Specifications ......................................................................................................... 33 Eye Diagram Measurement Setting....................................................................................................... 35 Power on/off and Power down specification ......................................................................................... 35 Optional functions ................................................................................................................................. 35 Pre-emphasis ................................................................................................................................. 35 Equalizer........................................................................................................................................ 35

3.6.1. 3.6.2. 4. 4.1.

Guideline for interoperability ........................................................................................................................ 36 Byte length and Color mapping............................................................................................................. 36

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V-by-One HS Standard_Ver.1.4 4.2. Multiple Data Lane combination........................................................................................................... 38 Allocation of pixel to Data Lane ................................................................................................... 38 Inter-lane skewing ......................................................................................................................... 40 RGB+CMY color mode................................................................................................................. 40 3D flag on blanking period............................................................................................................ 41 3D flag on DE active period .......................................................................................................... 42

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Abridged Edition

4.2.1. 4.2.2. 4.2.3. 4.3. 4.3.1. 4.3.2. 4.4. 5. 5.1. 5.2.

3D frame identification.......................................................................................................................... 41

Countermeasure against frequency change ........................................................................................... 43 Interoperability order of priority............................................................................................................ 44 Pin assignments ..................................................................................................................................... 49 Normal ground format ................................................................................................................... 49 Reduced ground format ................................................................................................................. 50 Electrical........................................................................................................................................ 53 Recommended Receptacle Interface Dimensions.......................................................................... 53

Connector and Cable ..................................................................................................................................... 44

5.2.1. 5.2.2. 5.3. 5.3.1. 5.3.2. 5.4. 6. 7. 8.

Connector Characteristics...................................................................................................................... 53

PCB Layout Considerations .................................................................................................................. 54

Glossary......................................................................................................................................................... 55 Revision history............................................................................................................................................. 56 Notice and Requires ...................................................................................................................................... 57

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V-by-One HS Standard_Ver.1.4

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Abridged Edition

1. Introduction
1.1. Objectives
V-by-One? HS targets a high speed data transmission of video signals based on internal connection of the equipment. V-by-One? HS pursues easier usage and lower power consumption compared with the current internal connection. V-by-One? HS supports up to 4Gbps data rate (effective data rate 3.2Gbps). V-by-One? HS supports scrambling and Clock Data Recovery (CDR) to reduce EMI. V-by-One? HS supports CDR to solve the skew problem between clock and data at conventional transfer system.

1.2. Technical Overview
With V-by-One? HS proprietary encoding scheme and CDR architecture, V-by-One? HS technology enables transmission up to 40bit video data, up to 24bit CTL data, HSYNC, VSYNC and Data Enable (DE) by some differential pair cables with minimal external components. As shown in Figure 1, V-by-One? HS Link includes Data Lanes, Hot Plug Detect signal (HTPDN), and CDR Lock signal (LOCKN). Number of Data Lanes is decided with the pixel rate and color depth (see Table 1). HTPDN connection between transmitter and receiver can be omitted as an application option. As optional functions, it is possible to implement transmitter pre-emphasis and receiver equalizer.
V-by-One HS Transmitter
TX0n TX0p TX1n TX1p
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V-by-One HS Receiver
RX0n RX0p RX1n RX1p

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Pixel Data

Pixel Data

...

Control Data
TXNn TXNp RXNn RXNp VDL 10kΩ HTPDN LOCKN HTPDN LOCKN

Control Data

Indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω

Figure 1

V-by-One? HS Link system Diagram

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V-by-One HS Standard_Ver.1.4

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1.2.1. Transmitter
V-by-One? HS Transmitter consists of packer, scrambler, encoder, serializer, and transmitter link monitor (Figure 3). Transmitter link monitor constantly monitor LOCKN and HTPDN signals. If the LOCKN signal is High, Transmitter executes the CDR training. Transmitter sends the CDR training pattern on the CDR training mode. When CDR locked, Transmitter shifts from CDR training mode to the normal mode, and then it starts to transmit input data from user logic.

1.2.2. Receiver
V-by-One? HS Receiver consists of unpacker, de-scrambler, decoder, de-serializer and receiver link monitor. The Receiver synchronizes the pixel clock while referring to the CDR training pattern on the CDR training mode. After shifting from the CDR training mode to the normal mode, the Receiver aligns byte and bit position using ALN training pattern. About ALN training, please refer to 2.2.5.2 in page 25).

1.2.3. Data Lane
Data Lane is AC-coupled differential pairs with termination. Transmission rate is able to be set up to 4Gbps depend on video pixel clock rate and bit depth. 1.2.3.1. Recommended data lane

Table 1
Resolution HD ex. 1280 x 720p Full HD ex. 1920 x 1080p Cinema Full HD ex. 2560 x 1080p 4K x 2K ex. 3840 x 2160p

Video data format vs. No of lane example
color depth 18/24/30/36 bit 18/24/30/36 bit 18/24/30/36 bit 18/24/30/36 bit 18/24/30/36 bit 18/24/30/36 bit 18/24/30/36 bit 18/24/30 bit 18/24/30 bit 18/24/30 bit 18/24/30/36 bit 18/24/30/36 bit 18/24/30/36 bit No of data lane* 1 2 4 2 4 8 16 2 4 8 8 16 32

Refresh rate (Pixel clock)

60Hz(74.25MHz) 120Hz(148.5MHz) 240Hz(297MHz) 60Hz(148.5MHz) 120Hz(297MHz) 240Hz(594MHz) 480Hz(1188MHz) 60Hz(185MHz) 120Hz(370MHz) 240Hz(740MHz) 60Hz(594MHz) 120Hz(1188MHz) 240Hz(2376MHz)

* Another lane number could be chosen; however, for the interoperability, those are STRONGLY recommended.

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V-by-One HS Standard_Ver.1.4

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1.2.3.2. Data lane consideration This chapter is informative only. It shows the procedure to select the minimum and maximum number of lanes necessary for the target application. As a 1st step, [byte mode] (please refer to 2.1.1.4) is chosen from 3, 4, or 5 depending upon color depth. Literally 3, 4, or 5 byte mode convey nominal 3, 4, or 5byte data. For example, 10bit per color RGB image requires 30 bit data per pixel; therefore, 4 byte mode which conveys 4 byte (32 bit) is enough to carry the data. As a 2nd step, total bit rate which is physically transmitted on V-by-One? HS line should be estimated. Because V-by-One? HS uses 8b10b encoding scheme, encoded data amount which is physically transmitted is 10bit per nominal decoded 8bit (1 byte) of original data. Multiplying [pixel clock] of the target application by encoded data amount per pixel results into [encoded total bit-rate] of V-by-One? HS transmission.

[encoded bit-rate per lane] can be calculated as [total bit rate] over [number of lanes] [number of lanes] should be chosen properly so that [encoded bit-rate per lane] is above 600Mbps and below 4Gbps.

[number of lanes] should be selected appropriate to signal handling in applications. For example, in case of video signal transmission, [number of lanes] is recommended to be divisor of Hactive, Hblank, and Htotal pixel number like 1, 2, 4, 8, etc. in order to help signal processing.

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V-by-One HS Standard_Ver.1.4

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Abridged Edition

1.2.4. HTPDN signal
HTPDN indicates connecting condition between the Transmitter and the Receiver. HTPDN of the transmitter side is High when the Receiver is not active or not connected. Then Transmitter can enter into the power down mode. HTPDN is set to Low by the Receiver when Receiver is active and connects to the Transmitter, and then Transmitter must start up and transmit CDR training pattern for link training. HTPDN is open drain output at the receiver side. Pull-up resistor is needed at the transmitter side. HTPDN connection between the Transmitter and the Receiver can be omitted as an application option. In this case, HTPDN at the Transmitter side should always be taken as Low.

V-by-One HS Transmitter
TX0n TX0p TX1n TX1p

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V-by-One HS Receiver
RX0n RX0p RX1n RX1p

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Pixel Data

Pixel Data

...

Control Data
TXNn TXNp RXNn RXNp

Control Data

VDL

10kΩ HTPDN LOCKN GND HTPDN LOCKN

Indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω

Figure 2

V-by-One? HS Link system without HTPDN connection schematic Diagram

1.2.5. LOCKN signal
LOCKN indicates whether the CDR PLL is in the lock state or not. LOCKN at the Transmitter input is set to High by pull-up resistor when Receiver is not active or at the CDR PLL training state. LOCKN is set to Low by the Receiver when CDR lock is done. Then the CDR training mode finishes and Transmitter shifts to the normal mode. LOCKN is open drain output at the receiver side. Pull-up resistor is needed at the transmitter side. When HTPDN is included in an application, the LOCKN signal should only be considered when the HTPDN is pulled low by the Receiver.

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V-by-One HS Standard_Ver.1.4

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Abridged Edition

4. Guideline for interoperability
In this chapter, guideline for interoperability is described.

The V-by-One? HS can be used to various types of color video format allocating D[39:0] to pixel data in packer and unpacker mapping. The color data mapping should refer to Table 11 and Table 12

4.1. Byte length and Color mapping

Table 11
Mode

RGB/YCbCr444/RGBW/RGBY color data mapping
40bpp RGBW / RGBY R[2] R[3] R[4] R[5] R[6] R[7] R[8] R[9] G[2] G[3] G[4] G[5] G[6] G[7] G[8] G[9] B[2] B[3] B[4] B[5] B[6] B[7] B[8] B[9] R[0] R[1] G[0] G[1] B[0] B[1] W/Y[0] W/Y[1] W/Y[2] W/Y[3] W/Y[4] W/Y[5] W/Y[6] W/Y[7] W/Y[8] W/Y[9] 32bpp RGBW / RGBY R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] G[0] G[1] G[2] G[3] G[4] G[5] G[6] G[7] B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] W/Y[0] W/Y[1] W/Y[2] W/Y[3] W/Y[4] W/Y[5] W/Y[6] W/Y[7]

Packer input & 36bpp RGB 30bpp RGB 24bpp RGB 18bpp RGB Unpacker output /YCbCr444 /YCbCr444 /YCbCr444 /YCbCr444 D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] D[15] D[16] D[17] D[18] D[19] D[20] D[21] D[22] D[23] D[24] D[25] D[26] D[27] D[28] D[29] D[30] D[31] D[32] D[33] D[34] D[35] D[36] D[37] D[38] D[39] R/Cr[4] R/Cr[5] R/Cr[6] R/Cr[7] R/Cr[8] R/Cr[9] R/Cr[10] R/Cr[11] G/Y[4] G/Y[5] G/Y[6] G/Y[7] G/Y[8] G/Y[9] G/Y[10] G/Y[11] B/Cb[4] B/Cb[5] B/Cb[6] B/Cb[7] B/Cb[8] B/Cb[9] B/Cb[10] B/Cb[11] (3DLR*) (3DEN*) B/Cb[2] B/Cb[3] G/Y[2] G/Y[3] R/Cr[2] R/Cr[3] B/Cb[0] B/Cb[1] G/Y[0] G/Y[1] R/Cr[0] R/Cr[1] R/Cr[2] R/Cr[3] R/Cr[4] R/Cr[5] R/Cr[6] R/Cr[7] R/Cr[8] R/Cr[9] G/Y[2] G/Y[3] G/Y[4] G/Y[5] G/Y[6] G/Y[7] G/Y[8] G/Y[9] B/Cb[2] B/Cb[3] B/Cb[4] B/Cb[5] B/Cb[6] B/Cb[7] B/Cb[8] B/Cb[9] (3DLR*) (3DEN*) B/Cb[0] B/Cb[1] G/Y[0] G/Y[1] R/Cr[0] R/Cr[1] R/Cr[0] R/Cr[1] R/Cr[2] R/Cr[3] R/Cr[4] R/Cr[5] R/Cr[6] R/Cr[7] G/Y[0] G/Y[1] G/Y[2] G/Y[3] G/Y[4] G/Y[5] G/Y[6] G/Y[7] B/Cb[0] B/Cb[1] B/Cb[2] B/Cb[3] B/Cb[4] B/Cb[5] B/Cb[6] B/Cb[7] R/Cr[0] R/Cr[1] R/Cr[2] R/Cr[3] R/Cr[4] R/Cr[5] G/Y[0] G/Y[1] G/Y[2] G/Y[3] G/Y[4] G/Y[5] B/Cb[0] B/Cb[1] B/Cb[2] B/Cb[3] B/Cb[4] B/Cb[5] -

Byte0

3byte mode

Byte1

5byte mode

4byte mode

Byte2

Byte3

Byte4

* Implementation specific

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V-by-One HS Standard_Ver.1.4

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Abridged Edition
Table 12
Mode

YCbCr422 color data mapping
32bpp YCbCr422 24bpp YCbCr422 20bpp YCbCr422 Cb/Cr[2] Cb/Cr[3] Cb/Cr[4] Cb/Cr[5] Cb/Cr[6] Cb/Cr[7] Cb/Cr[8] Cb/Cr[9] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Y[8] Y[9] Y[0] Y[1] Cb/Cr[0] Cb/Cr[1] 16bpp YCbCr422 Cb/Cr[0] Cb/Cr[1] Cb/Cr[2] Cb/Cr[3] Cb/Cr[4] Cb/Cr[5] Cb/Cr[6] Cb/Cr[7] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] -

Packer input & Unpacker output D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] D[15] D[16] D[17] D[18] D[19] D[20] D[21] D[22] D[23] D[24] D[25] D[26] D[27] D[28] D[29] D[30] D[31] D[32] D[33] D[34] D[35] D[36] D[37] D[38] D[39]

Byte0

Byte1

Byte2

Byte3

Byte4

Cb/Cr[8] Cb/Cr[4] Cb/Cr[9] Cb/Cr[5] Cb/Cr[10] Cb/Cr[6] Cb/Cr[11] Cb/Cr[7] Cb/Cr[12] Cb/Cr[8] Cb/Cr[13] Cb/Cr[9] Cb/Cr[14] Cb/Cr[10] Cb/Cr[15] Cb/Cr[11] Y[8] Y[4] Y[9] Y[5] Y[10] Y[6] Y[11] Y[7] Y[12] Y[8] Y[13] Y[9] Y[14] Y[10] Y[15] Y[11] Y[2] Y[3] Cb/Cr[2] Cb/Cr[3] Y[6] Y[2] Y[7] Y[3] Cb/Cr[6] Cb/Cr[2] Cb/Cr[7] Cb/Cr[3] Y[0] Y[1] Cb/Cr[0] Cb/Cr[1] Y[4] Y[0] Y[5] Y[1] Cb/Cr[4] Cb/Cr[0] Cb/Cr[5] Cb/Cr[1]

5byte mode

4byte mode

3byte mode

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V-by-One HS Standard_Ver.1.4

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4.2. Multiple Data Lane combination
4.2.1. Allocation of pixel to Data Lane
Depend on the data rate and pixel color depth, it is permitted to increase the Data Lanes. About the multiple Data Lanes combination, refers to Figure 27 as first recommendation. For multiple device transmission, signal space can be divided into multiple sections vertically described in the following pages and figures. The V-by-One? HS compliant components must be implemented with at least one Data Lane. If the data rate of the required color depth and timing is higher than the components maximum supported data rate, additional Data Lane can be used. (The maximum data rate of V-by-One? HS Data Lane is 4Gbps per lane and the minimum is 600Mbps.) In this case, total lane count should be even number, under the condition of the fewer lane number. The pixel number for the horizontal active and blanking term (Hactive, Hblank) should be adjusted to become the multiple number of the lane count.
Lane 0 ? FSBS FSBP* ? FSBP FSBE_SR Pixel 1** Pixel N+1 ? ? ? FSBS FSBP ? FSBP FSBE Pixel 1 Pixel N+1 ? ? ? FSBS | | | FSBE_SR Lane 1 ? FSBS FSBP* ? FSBP FSBE_SR Pixel 2** Pixel N+2 ? ? ? FSBS FSBP ? FSBP FSBE Pixel 2 Pixel N+2 ? ? ? FSBS | | | FSBE_SR Lane 2 ? FSBS FSBP* ? FSBP FSBE_SR Pixel 3** Pixel N+3 ? ? ? FSBS FSBP ? FSBP FSBE Pixel 3 Pixel N+3 ? ? ? FSBS | | | FSBE_SR ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? Lane N-1 ? FSBS FSBP* ? FSBP FSBE_SR Pixel N** Pixel 2N ? ? ? FSBS FSBP ? FSBP FSBE Pixel N Pixel 2N ? ? ? FSBS | | | FSBE_SR

V Blank

Line 1

H Blank

Line 2 | | | | | | |

* The 1st pixel of each lane FSBP in vertical blanking period may convey 3D flag of next frame with particular assigned CTL bit ** The 1st pixel of each lane in a frame may convey 3D flag of current frame with particular assigned bit 3DLR and 3DEN

Figure 27

Allocation of pixel to Data Lane

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V-by-One HS Standard_Ver.1.4

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Lane 0 ? FSBS FSBP* ? FSBP FSBE_SR
Pixel 1** Pixel N/M+1

V Blank

Lane 1 ? FSBS FSBP* ? FSBP FSBE_SR
Pixel 2** Pixel N/M+2

Line 1

H Blank

? ? ? FSBS FSBP ? FSBP FSBE
Pixel 1 Pixel N/M+1

? ? ? FSBS FSBP ? FSBP FSBE
Pixel 2 Pixel N/M+2

Line 2 | | | | | | |

? ? ? FSBS | | | FSBE_SR

? ? ? FSBS | | | FSBE_SR

??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ???

Lane N/M-1 ? FSBS FSBP* ? FSBP FSBE_SR
Pixel N/M** Pixel 2N/M

Lane N/M ? FSBS FSBP* ? FSBP FSBE_SR
Pixel H/M+1** Pixel H/M+N/M+1

Lane N/M+1 ? FSBS FSBP* ? FSBP FSBE_SR
Pixel H/M+2** Pixel H/M+N/M+2

? ? ? FSBS FSBP ? FSBP FSBE
Pixel N/M Pixel 2N/M

? ? ? FSBS FSBP ? FSBP FSBE
Pixel H/M+1 Pixel H/M+N/M+1

? ? ? FSBS FSBP ? FSBP FSBE
Pixel H/M+2 Pixel H/M+N/M+2

? ? ? FSBS | | | FSBE_SR

? ? ? FSBS | | | FSBE_SR

? ? ? FSBS | | | FSBE_SR

??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ???

Lane N-1 ? FSBS FSBP* ? FSBP FSBE_SR
Pixel (M-1)H/M+N/M** Pixel (M-1)H/M+2N/M

? ? ? FSBS FSBP ? FSBP FSBE
Pixel (M-1)H/M+N/M Pixel (M-1)H/M+2N/M

? ? ? FSBS | | | FSBE_SR

* The 1st pixel of each lane FSBP in vertical blanking period may convey 3D flag of next frame with particular assigned CTL bit ** The 1st pixel of each lane in a frame may convey 3D flag of current frame with particular assigned bit 3DLR and 3DEN

Figure 28

N lane data with M section allocation in frame (Horizontal active : H pixels)

V Blank

Line 1 H Blank Line 2

Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7 FSBS FSBS FSBS FSBS FSBS FSBS FSBS FSBS FSBP* FSBP* FSBP* FSBP* FSBP* FSBP* FSBP* FSBP* ? ? ? ? ? ? ? ? FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR FSBE_SR Pixel 1** Pixel 2** Pixel 481** Pixel 482** Pixel 961** Pixel 962** Pixel 1441** Pixel 1442** Pixel 3 Pixel 4 Pixel 483 Pixel 484 Pixel 963 Pixel 964 Pixel 1443 Pixel 1444 ? ? ? ? ? ? ? ? Pixel 479 Pixel 480 Pixel 959 Pixel 960 Pixel 1439 Pixel 1440 Pixel 1919 Pixel 1920 FSBS FSBS FSBS FSBS FSBS FSBS FSBS FSBS ? ? ? ? ? ? ? ? FSBE FSBE FSBE FSBE FSBE FSBE FSBE FSBE Pixel 1 Pixel 2 Pixel 481 Pixel 482 Pixel 961 Pixel 962 Pixel 1441 Pixel 1442 Pixel 3 Pixel 4 Pixel 483 Pixel 484 Pixel 963 Pixel 964 Pixel 1443 Pixel 1444 ? ? ? ? ? ? ? ? Pixel 479 Pixel 480 Pixel 959 Pixel 960 Pixel 1439 Pixel 1440 Pixel 1919 Pixel 1920 FSBS FSBS FSBS FSBS FSBS FSBS FSBS FSBS * The 1st pixel of each lane FSBP in vertical blanking period may convey 3D flag of next frame with particular assign ** The 1st pixel of each lane in a frame may convey 3D flag of current frame with particular assigned bit 3DLR and 3

Figure 29

8 lane data with 4 section allocation example (Horizontal active : 1920 pixels)

For the DTV application, Data Lane number in Table 1 is STRONGLY recommended for interoperability.

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4.2.2. Inter-lane skewing
Allowable Inter-lane skew is defined as tRISK. Refer to Section 3.3. V-by-One? HS Transmitter is not required to make any intentional inter-lane skew between lanes.

4.2.3. RGB+CMY color mode
If the Transmitter and the Receiver adopt the RGB+CMY (6 color mode) transmission, twice of the lanes are used for the RGB and CMY. In the CMY lanes, the positions of the C data, M data, and Y data are mapped at the positions of the R data, G data, and B data in the Table 11, respectively.

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4.3. 3D frame identification
3D display may have identification on every frame. Methods to label 3D information on frame are described. The description of 3D data allocation in this chapter is informative. Actual application may be different. 2 possible alternatives are introduced in this chapter; however, to apply both methods at the same time does not have to be required. Users have to choose one explicit method for their application.

4.3.1. 3D flag on blanking period
Packer and Unpacker data mapping in Table 2 and Table 3 show that there is a potential to send arbitrary data on V-by-One? HS during blanking period. One way to carry 3D information is to make use of CTL data mapping. Use of CTL<1:0> is implementation specific. 4.3.1.1. CTL data allocation to 3D flag It is suggested that CTL<0> and CTL<1> be used for 3D signaling. These signals correspond to CTL<1:0> in Table 2 and Table 3. CTL<0> = Left/Right Indicator CTL<0> = high (1) the next frame is the Left View CTL<0> = low (0) the next frame is the Right View CTL<1> = 3D Mode Enable CTL<1> = high (1) 3D video is being transmitted CTL<1> = low (0) 2D video is being transmitted 4.3.1.2. CTL data timing of 3D flag CTL<1:0> of the first pixel of the FSBP on each lane in vertical blanking period is recommended to be used for processing on receiver side. It is recommended to apply to the active video that immediately follows the vertical blanking period.

1st FSBP on each lane in V blank CTL<0>=0, CTL<1>=0 Blanking period The next frame is 2D video

1st FSBP on each lane in V blank CTL<0>=1, CTL<1>=1 Blanking period The next frame is 3D video Left view

1st FSBP on each lane in V blank CTL<0>=0, CTL<1>=1 Blanking period The next frame is 3D video Right view

Active period

Active period

Active period

Figure 30

Schematic diagram of 3D flag on blanking period

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4.3.2. 3D flag on DE active period
The color data mapping in Table 11 and Table 12 show that there are unused bits depending on the colors and byte mode used. It is possible (and allowable) to make use of these unused bits to carry the 3D information. Use of 3DLR and 3DEN is implementation specific. 4.3.2.1. Color data mapping allocation to 3D flag 3D information can be conveyed using the 3DLR and 3DEN bits in Table 11 The 30bpp RGB/CrYCb 4 byte mode and 36bpp RGB/CrYCb 5 byte of Table 11 show the recommended placement of these controls. 3DLR = Left/Right Indicator 3DLR = high (1) the next frame is the Left View 3DLR = low (0) the next frame is the Right View 3DEN = 3D Mode Enable 3DEN = high (1) 3D video is being transmitted 3DEN = low (0) 2D video is being transmitted 4.3.2.2. Color data mapping timing of 3D flag 3DLR and 3DEN of the first pixel on each lane in particular frame is recommended to be used for processing. It is recommended to apply 3D flag to the current frame.

1st pixel on each lane in DE active 3DLR=0, 3DEN=0 Blanking period Current frame is 2D video

1st pixel on each lane in DE active 3DLR=1, 3DEN=1 Blanking period Current frame is 3D video Left view

1st pixel on each lane in DE active 3DLR=0, 3DEN=1 Blanking period Current frame is 3D video Right view

Active period

Active period

Active period

Figure 31

Schematic diagram of 3D flag on DE active period

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4.4. Countermeasure against frequency change
Some system has unavoidable frequency change during operation when it is supposed to keep particular frequency for continuous stream. Because V-by-One? HS is the signal stream whose speed depending on inputted clock frequency, this frequency change during operation can result into undesired visible error. In order to avoid harmful situation, possible options are presented in this section. First method is to stop data stream completely as described in 2.2.4 case (a) before changing frequency and restart link with the new frequency. This method can avoid signal unstable period in whole system. Second method is to make frequency anomaly slow and easy enough even if it is undesired when it is originally supposed to keep particular frequency. Third method is to place short time frequency anomaly occasion on long enough invisible blanking period when it is originally supposed to keep particular frequency. Frequency shift may cause unstable signal and require recovery time, while blanking period could prevent this unstable situation from actual visible experience at maximum extent. Possible example is shown below. Early stage of FSBP in vertical blanking period is one reasonable recommended option for frequency change occasion.
CLK Vsync Hsync DE
Framing Symbol
FSBP FSBE FSACTIVE FSBS FSBP FSBE FSACTIVE FSBS

???

???

???

??? ??? Vertical blanking period ??? ???

???

??? ??? Freq. change had better be in early stage of Vblank FSBP. ??? ???
FSBE_SR
FSBP FSACTIVE FSBS

Figure 32

Frequency change timing control recommendation

Those method described in this section requires understanding of not only discrete device implementer but also whole system architect and especially designer of transmitter or signal source device.

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5. Connector and Cable
This chapter shows guideline of connector and cable to connect the V-by-One? HS Transmitter (ex. video processing unit) and Receiver (ex. Panel module).

5.1. Interoperability order of priority
For interoperability, the following points are STRONGLY RECOMMENDED to be paid attention to. Pin assignment for V-by-One? HS transmission is absolutely irreplaceable and must be fixed. V-by-One? HS Hot plug detect V-by-One? HS Lock detect V-by-One? HS CML Ground V-by-One? HS Lane The following is an example of 8 lane case. V-by-One? HS related pin assignment must be kept.

Table 13
Pin No. 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Irreplaceable V-by-One HS transmission signal on 8 Lane Pin Assignment
Tx Symbol Vcc Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) HTPDN LOCKN CML GND Tx0n Tx0p CML GND CML GND Tx1n Tx1p CML GND CML GND Tx2n Tx2p CML GND CML GND Tx3n Tx3p CML GND CML GND Tx4n Tx4p CML GND CML GND Tx5n Tx5p CML GND CML GND Tx6n Tx6p CML GND CML GND Tx7n Tx7p CML GND (Option) (Option) Supply voltage for module Supply voltage for module Supply voltage for module Supply voltage for module (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) V-by-One HS Hot plug detect V-by-One HS Lock detect V-by-One HS CML Ground V-by-One HS Lane0 (CML) V-by-One HS Lane0 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane1 (CML) V-by-One HS Lane1 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane2 (CML) V-by-One HS Lane2 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane3 (CML) V-by-One HS Lane3 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane4 (CML) V-by-One HS Lane4 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane5 (CML) V-by-One HS Lane5 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane6 (CML) V-by-One HS Lane6 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane7 (CML) V-by-One HS Lane7 (CML) V-by-One HS CML Ground (User option) (User option) Description Symbol Vcc Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) HTPDN LOCKN CML GND Rx0n Rx0p CML GND CML GND Rx1n Rx1p CML GND CML GND Rx2n Rx2p CML GND CML GND Rx3n Rx3p CML GND CML GND Rx4n Rx4p CML GND CML GND Rx5n Rx5p CML GND CML GND Rx6n Rx6p CML GND CML GND Rx7n Rx7p CML GND (Option) (Option) Rx Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

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V-by-One HS Standard_Ver.1.4 If power is supplied, the following rules must be kept. It must be placed from Rx pin No. 1 to Rx pin No. x .with sufficient number required. Minimum number of power is standard defined and another (Option) pins can be added to power. The following is an example of 8 lane case. power supply pin assignment must be from Rx pin No. 1. Table 14 Irreplaceable power supply pins on 8 Lane Pin Assignment
Tx Pin No. 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Symbol Vcc Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) HTPDN LOCKN CML GND Tx0n Tx0p CML GND CML GND Tx1n Tx1p CML GND CML GND Tx2n Tx2p CML GND CML GND Tx3n Tx3p CML GND CML GND Tx4n Tx4p CML GND CML GND Tx5n Tx5p CML GND CML GND Tx6n Tx6p CML GND CML GND Tx7n Tx7p CML GND (Option) (Option) Supply voltage for module Supply voltage for module Supply voltage for module Supply voltage for module (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) V-by-One HS Hot plug detect V-by-One HS Lock detect V-by-One HS CML Ground V-by-One HS Lane0 (CML) V-by-One HS Lane0 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane1 (CML) V-by-One HS Lane1 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane2 (CML) V-by-One HS Lane2 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane3 (CML) V-by-One HS Lane3 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane4 (CML) V-by-One HS Lane4 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane5 (CML) V-by-One HS Lane5 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane6 (CML) V-by-One HS Lane6 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane7 (CML) V-by-One HS Lane7 (CML) V-by-One HS CML Ground (User option) (User option) Description Symbol Vcc Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) HTPDN LOCKN CML GND Rx0n Rx0p CML GND CML GND Rx1n Rx1p CML GND CML GND Rx2n Rx2p CML GND CML GND Rx3n Rx3p CML GND CML GND Rx4n Rx4p CML GND CML GND Rx5n Rx5p CML GND CML GND Rx6n Rx6p CML GND CML GND Rx7n Rx7p CML GND (Option) (Option) Rx Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

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Abridged Edition

If system need more power supply line, another pins can be attached from (options) to power pin assignment. Table 15 Expanded power supply example on 8 Lane Pin Assignment
Tx Pin No. 51 50 49 48 47 46 45 44 43 42-1 Symbol Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc (Option) Supply voltage for module Supply voltage for module Supply voltage for module Supply voltage for module Supply voltage for module (Added) Supply voltage for module (Added) Supply voltage for module (Added) Supply voltage for module (Added) (User option) Description Symbol Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc (Option) Rx Pin No. 1 2 3 4 5 6 7 8 9 10-51

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V-by-One HS Standard_Ver.1.4 Pins originally assigned to (User option) can be used for any purpose. It can be another power supply in order to support consumption. It can be ground to stabilize power supply and V-by-One? HS transmission more. Power ground pins assigned to (User option) should be beside power supply beyond 1 N/C pin It can be another control signals like I2C, SPI, GPIO or other user defined transmission. If there is remainder of (Option) pins, those are supposed to be assigned to ground. The following is an example of 8 lane case. There are 13 user option pins which can be used arbitrary.

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Abridged Edition

Table 16
Tx Pin No. 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Symbol

Multi purpose user option pins on 8 Lane Pin Assignment
Description Symbol Supply voltage for module Supply voltage for module Supply voltage for module Supply voltage for module (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) V-by-One HS Hot plug detect V-by-One HS Lock detect V-by-One HS CML Ground V-by-One HS Lane0 (CML) V-by-One HS Lane0 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane1 (CML) V-by-One HS Lane1 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane2 (CML) V-by-One HS Lane2 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane3 (CML) V-by-One HS Lane3 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane4 (CML) V-by-One HS Lane4 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane5 (CML) V-by-One HS Lane5 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane6 (CML) V-by-One HS Lane6 (CML) V-by-One HS CML Ground V-by-One HS CML Ground V-by-One HS Lane7 (CML) V-by-One HS Lane7 (CML) V-by-One HS CML Ground (User option) (User option) Vcc Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) HTPDN LOCKN CML GND Rx0n Rx0p CML GND CML GND Rx1n Rx1p CML GND CML GND Rx2n Rx2p CML GND CML GND Rx3n Rx3p CML GND CML GND Rx4n Rx4p CML GND CML GND Rx5n Rx5p CML GND CML GND Rx6n Rx6p CML GND CML GND Rx7n Rx7p CML GND (Option) (Option) Rx Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Vcc Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) HTPDN LOCKN CML GND Tx0n Tx0p CML GND CML GND Tx1n Tx1p CML GND CML GND Tx2n Tx2p CML GND CML GND Tx3n Tx3p CML GND CML GND Tx4n Tx4p CML GND CML GND Tx5n Tx5p CML GND CML GND Tx6n Tx6p CML GND CML GND Tx7n Tx7p CML GND (Option) (Option)

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V-by-One HS Standard_Ver.1.4 Multiple Rx PCBs with standard pin assignment can be connected to single carefully designed Tx PCB. Irreplaceable V-by-One?HS lines without HTPDN are supposed to be simply linked to Tx PCB node Tx HTPDN node should have two options to be connected to FFC or to be connected to Tx PCB GND Irreplaceable power supply lines are supposed to be simply linked to Tx PCB node (Option) pins are supposed to be linked to PCB node via passive component (ex. 0ohm Resistor) Tx PCB can be carefully designed in order to realize multi Rx supplier system with parts mount

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Abridged Edition

Figure 33

HTPDN circuit on Tx PCB to multiple Rx PCBs

The following two examples are of 8 lane case. Two standard recommended assignments are shown. Tx side PCB is the same one for both case, while Rx side PCB is different; however, both follows the Standard. Mounting or unmounting passive component on Tx PCB can realize multiple Rx PCB accommodation.

Table 17
Pin No. 51-50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35-4 3 2 1

Tx PCB arrangement example to Rx PCB #1 on 8 Lane Pin Assignment
Tx PCB arrangement condition Symbol Supply voltage for module Supply voltage for module Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB Not connected Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB V-by-One HS CML Ground Not Connected by unmounting part on Tx PCB Not Connected by unmounting part on Tx PCB Vcc Vcc Vcc Vcc Vcc N/C GND GND GND SCL SDA DC control DC control HTPDN CML GND GND GND Rx Pin No. 1-2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17-48 49 50 51 Symbol Vcc Vcc Vcc Vcc Vcc N/C GND GND GND SCL SDA DC control DC control HTPDN CML GND SCL SDA

Tx PCB Node via series resistor

Figure 34

Tx PCB arrangement example to Rx PCB #1 on 8 Lane Pin Assignment

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Tx PCB arrangement example to Rx PCB #2 on 8 Lane Pin Assignment
Tx PCB arrangement condition Symbol Supply voltage for module Supply voltage for module Connected by mounting part on Tx PCB Not Connected by unmounting part on Tx PCB Not Connected by unmounting part on Tx PCB Not connected Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB Not Connected by unmounting part on Tx PCB Not Connected by unmounting part on Tx PCB Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB V-by-One HS CML Ground Connected by mounting part on Tx PCB Connected by mounting part on Tx PCB Vcc Vcc Vcc N/C GND GND GND GND GND DC control DC control DC control DC control HTPDN CML GND SCL SDA Rx Pin No. 1-2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17-48 49 50 51 Symbol Vcc Vcc Vcc Vcc Vcc N/C GND GND GND SCL SDA DC control DC control HTPDN CML GND SCL SDA Tx PCB Node via series resistor Pin No. 51-50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35-4 3 2 1

Table 18

Tx PCB node 51-50 49 Vcc 48 Vcc 47 Vcc 46 Vcc 45 Vcc 44 N/C 43 GND 42 GND 41 GND 40 SCL 39 SDA 38 DC control 37 DC control 36 HTPDN 35-4 3 GND 2 SCL 1 SDA

Pin# from Rx 51-50 49 Vcc 48 Vcc 47 Vcc 46 N/C 45 GND 44 GND 43 GND 42 GND 41 GND 40 DC control 39 DC control 38 DC control 37 DC control 36 HTPDN 35-4 3 GND 2 SCL 1 SDA

51pin Connector

51pin Connector

#51

#1

51pin Connector

V-by-One? HS 8lane Tx

FFC
#1 #51

V-by-One? HS 8lane Rx

Tx PCB #0

Rx PCB #2

Figure 35

Tx PCB arrangement example to Rx PCB #1 on 8 Lane Pin Assignment

Just for more information, Tx side PCB can also be designed to reverse pin assignment. For example, [pin #41 SCL, pin #42 SDA] can be inverted to [pin #41 SDA, pin #42 SCL] with carefully designed PCB and mounting several passive components at the same time.

Figure 36

Circuit to reverse Pin Assignment on Tx PCB

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5.2. Pin assignments
5.2.1. Normal ground format
1,2,4, and 8-Lane pin assignments are shown below.

Table 19
Normal CML GND Format Pin No. to Panel (Rx) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Normal CML Ground Format Pin Assignment
FHD60Hz RGB30bit 21pins Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (HTPDN*) LOCKN CML GND Rx0n Rx0p CML GND CML GND Rx1n Rx1p CML GND (Option) (Option) FHD120Hz RGB30bit 31pins Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (HTPDN*) LOCKN CML GND Rx0n Rx0p CML GND CML GND Rx1n Rx1p CML GND CML GND Rx2n Rx2p CML GND CML GND Rx3n Rx3p CML GND (Option) (Option) FHD240Hz RGB30bit 51pins Vcc Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (HTPDN*) LOCKN CML GND Rx0n Rx0p CML GND CML GND Rx1n Rx1p CML GND CML GND Rx2n Rx2p CML GND CML GND Rx3n Rx3p CML GND CML GND Rx4n Rx4p CML GND CML GND Rx5n Rx5p CML GND CML GND Rx6n Rx6p CML GND CML GND Rx7n Rx7p CML GND (Option) (Option)

HD60Hz RGB30bit 21pins Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (HTPDN*) LOCKN CML GND Rx0n Rx0p CML GND (Option) (Option) (Option) (Option) (Option) (Option)

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5.2.2. Reduced ground format
Some system requires both a lot of user option signals or power supply pins and a lot of lanes at the same time. For that case, reduced CML ground format is presented. Around maximum speed transmission, this reduced ground format gives only slight margin; therefore, users must pay attentions to transmitter and receiver characteristics, PCB design, and connector/harness selection so that receiver side Eye-Diagram is wide enough to establish V-by-One? HS transmission. Table 20 8 Lane Connector Reduced CML Ground Format Pin Assignment
Tx Pin No. 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Symbol Vcc Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (HTPDN*) LOCKN CML GND Tx0n Tx0p CML GND Tx1n Tx1p CML GND Tx2n Tx2p CML GND Tx3n Tx3p CML GND Tx4n Tx4p CML GND Tx5n Tx5p CML GND Tx6n Tx6p CML GND Tx7n Tx7p CML GND Supply voltage for module Supply voltage for module Supply voltage for module Supply voltage for module (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (User option) (V-by-One HS Hot plug detect*) V-by-One HS Lock detect V-by-One HS CML Ground V-by-One HS Lane0 (CML) V-by-One HS Lane0 (CML) V-by-One HS CML Ground V-by-One HS Lane1 (CML) V-by-One HS Lane1 (CML) V-by-One HS CML Ground V-by-One HS Lane2 (CML) V-by-One HS Lane2 (CML) V-by-One HS CML Ground V-by-One HS Lane3 (CML) V-by-One HS Lane3 (CML) V-by-One HS CML Ground V-by-One HS Lane4 (CML) V-by-One HS Lane4 (CML) V-by-One HS CML Ground V-by-One HS Lane5 (CML) V-by-One HS Lane5 (CML) V-by-One HS CML Ground V-by-One HS Lane6 (CML) V-by-One HS Lane6 (CML) V-by-One HS CML Ground V-by-One HS Lane7 (CML) V-by-One HS Lane7 (CML) V-by-One HS CML Ground Description Symbol Vcc Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (HTPDN*) LOCKN CML GND Rx0n Rx0p CML GND Rx1n Rx1p CML GND Rx2n Rx2p CML GND Rx3n Rx3p CML GND Rx4n Rx4p CML GND Rx5n Rx5p CML GND Rx6n Rx6p CML GND Rx7n Rx7p CML GND Rx Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

* HTPDN connection can be eliminated in prepared system and turn it into ground or other user options.
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V-by-One HS Standard_Ver.1.4 4,8,16, 32 Lane pin assignments are shown below.

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Abridged Edition

Table 21
Reduced CML GND Format Pin No. to Panel (Rx) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Reduced CML Ground Format Pin Assignment
FHD240Hz RGB30bit 51pins Vcc Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (HTPDN*) LOCKN CML GND Rx0n Rx0p CML GND Rx1n Rx1p CML GND Rx2n Rx2p CML GND Rx3n Rx3p CML GND Rx4n Rx4p CML GND Rx5n Rx5p CML GND Rx6n Rx6p CML GND Rx7n Rx7p CML GND 4K2K120Hz RGB30bit 51pins 41pins Vcc Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (HTPDN*) LOCKN CML GND Rx0n Rx0p CML GND Rx1n Rx1p CML GND Rx2n Rx2p CML GND Rx3n Rx3p CML GND Rx4n Rx4p CML GND Rx5n Rx5p CML GND Rx6n Rx6p CML GND Rx7n Rx7p CML GND CML GND Rx8n Rx8p CML GND Rx9n Rx9p CML GND Rx10n Rx10p CML GND Rx11n Rx11p CML GND Rx12n Rx12p CML GND Rx13n Rx13p CML GND Rx14n Rx14p CML GND Rx15n Rx15p CML GND (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option)

FHD120Hz RGB30bit 41pins Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (HTPDN*) LOCKN CML GND Rx0n Rx0p CML GND Rx1n Rx1p CML GND Rx2n Rx2p CML GND Rx3n Rx3p CML GND (Option) (Option)

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Abridged Edition
Table 22 Reduced CML Ground Format Pin Assignment (Continue)
51pins Vcc Vcc Vcc Vcc (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (Option) (HTPDN*) LOCKN CML GND Rx0n Rx0p CML GND Rx1n Rx1p CML GND Rx2n Rx2p CML GND Rx3n Rx3p CML GND Rx4n Rx4p CML GND Rx5n Rx5p CML GND Rx6n Rx6p CML GND Rx7n Rx7p CML GND 4K2K240Hz RGB30bit 41pins CML GND Rx8n Rx8p CML GND Rx9n Rx9p CML GND Rx10n Rx10p CML GND Rx11n Rx11p CML GND Rx12n Rx12p CML GND Rx13n Rx13p CML GND Rx14n Rx14p CML GND Rx15n Rx15p CML GND Rx16n Rx16p CML GND Rx17n Rx17p CML GND Rx18n Rx18p CML GND Rx19n Rx19p CML GND (Option) (Option) (Option) (Option) 41pins CML GND Rx20n Rx20p CML GND Rx21n Rx21p CML GND Rx22n Rx22p CML GND Rx23n Rx23p CML GND Rx24n Rx24p CML GND Rx25n Rx25p CML GND Rx26n Rx26p CML GND Rx27n Rx27p CML GND Rx28n Rx28p CML GND Rx29n Rx29p CML GND Rx30n Rx30p CML GND Rx31n Rx31p CML GND (Option) (Option) (Option) (Option) Reduced CML GND Format Pin No. to Panel (Rx) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Note: Some cable like Flexible Printed Circuits (FPC) does not have the symmetric conductor layout. This means that if users connect the cable at reverse direction, i.e. Rx plug is connected to Transmitter’s receptacle and Tx plug to Receiver’s receptacle, the correct connection cannot be achieved. Users must take care with the cable direction.

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5.3. Connector Characteristics
5.3.1. Electrical
Operating Current : 0.5A per pin minimum Operating Voltage : 150VAC rms, maximum Voltage proof : 200 VAC for minimum of 1 minute

5.3.2. Recommended Receptacle Interface Dimensions
0.5mm signal terminal pitch connector is recommended for interoperability.

(a) Drawings

(b) Footprint

Figure 37

PCB Mount Receptacle drawings (recommended) Table 23 Form Factor of Receptacle

No. of CONTACT 21 31 41 51

A 22.85 27.85 32.85 37.85

B 20.46 25.46 30.46 35.46

C 16 21 26 31

D 10 15 20 25

E 10 15 20 25

F 16 21 26 31

G 10 15 20 25

H 19.75 24.75 29.75 34.75

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5.4. PCB Layout Considerations
Use at least 4-layer PCB with signals, GND, power, and signals assigned for each layer. (Refer to figure below.) PCB traces for the high-speed signals must be single-ended microstrip lines or coupled microstrip lines whose differential characteristic impedance is 100?. Minimize the distance between traces of a differential pair (S1 of Figure 38) to maximize common mode rejection and coupling effect which works to reduce Electro-Magnetic Interference (EMI). Route differential signal traces symmetrically. Avoid right-angle turns or minimize the number of vias on the high speed traces because they usually cause impedance discontinuity in the transmission lines and degrade the signal integrity. Mismatch among impedances of PCB traces, connectors, or cables also caused reflection, limiting the bandwidth of the high-speed Lanes.

PCB Cross-sectional View for Microstrip Lines
> 3 x S1 S1 > 3 x S1

GND Layer1: Signals Layer2: GND Layer3: Power Layer4: Signals

GND

Figure 38

PCB Cross-sectional View for Microstrip Lines

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6. Glossary
Table 24 Glossary of Terms
Data Lane framing symbol Byte mode Character One differential signal line FSACTIVE, FSBS, FSBP, FSBE, and FSBE_SR are the framing symbols. One framing symbol is transmitted at the one pixel clock The size of framing symbols is decided by the byte mode 3,4, and 5 byte mode is prepared. The byte mode is decided by the color depth and color format (RGB or YCbCr etc.) 8 bit data before 8b/10 encoder and after 10b/8b decoder 10 bit data after 8b/10 encoder and before 10b/8b decoder In addition to the pixel data, special character is assigned. See Table 4.

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7. Revision history
Date 2008/5/26 Version Ver 1.0 Original (obsolete) The color mapping is changed. The order of the pin assignment is changed. PLL loop bandwidth of the Transmitter is defined. Electrical specifications are described for LOCKN and HTPDN. Clarify the Inter-pair skew and Intra-pair skew specifications. RGBY and RGB+CMY is added to the color mapping. Inter lane skew is specified in the chapter 4.2.2. Collected the Training pattern (D10.2) frequency for link training in chapter 2.4.5.1 CDR training. Organization and Wording correction and clarification. (obsolete) The range of VDL is extended, and VOL spec. is changed. The behavior of the Scrambler is corrected. Correction of the value in tRISK_INTRA and tRISK_INTER. The Eye Diagram and CML Jitter at Transmitter are relaxed. Clarify the Receiver eye measurement point. Correction of the range of tTBIT and tRBIT. Correction of some typo. Scrambler/descrambler chart is corrected. LFSR proceeds with K code. Vsync “1” in ALN Training allocation is corrected to 4th last pixel. ALN Training period per lane is fixed independent of lane counts. No HTPDN connection option is introduced. Basic receiver Eye-Diagram measurement point is at CML input pins. Transmitter intra-pair skew accuracy definition is conditioned and relaxed. Examples of lane number according to format (2560x1080p, 480Hz) are added. Guideline of frame ID transmission method for 3D display is added Receiver side Eye-Diagram measurement CDR setting explanation is added. Data lane consideration chapter is added. Section “Cable Characteristics” is deleted. Recommended approach to interoperable pin assignment is explained. 16 lane connection pin assignment guideline is added. Discrepancy of pulled up voltage is corrected. Description of FSBE_SR is clarified. Connector form factor of 51 pins receptacle is added. Page numbers on table of contents are corrected. Correction of some typo. Some descriptions are added. Maximum speed is enlarged to 4Gbps. Transmitter output under Tx PLL unstable condition is defined to be fixed. Countermeasure against frequency change is additionally described. Reduced pin number pin assignment guideline is added. HTPDN/LOCKN detection voltages are loosend. Multiple vertical section transmission mode guideline is additionally described. Freedom of polarity about DE, Vsync, and Hsync is explicitly described. Detailed measurement method of Tx EYE diagram is additionally described. 3D flag and its timing description is additionally described. Recommended approach to interoperable pin assignment is re-defined. Correction of some typo. Some descriptions are altered or added

2008/11/22

Ver 1.1

2009/1/15

Ver. 1.2

2010/07/07

Ver.1.3

2011/12/15

Ver.1.4

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8. Notice and Requires
1. THIS DOCUMENT AND RELATED MATERIALS AND INFORMATION ARE PROVIDED "AS IS" WITH NO WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE. THINE ASSUMES NO RESPONSIBILITY FOR ANY ERRORS CONTAINED IN THIS DOCUMENT AND HAS NO LIABILITIES OR OBLIGATIONS FOR ANY DAMAGES ARISING FROM OR IN CONNECTION WITH THE USE OF THIS DOCUMENT. 2. THine may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppels or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. 3. This material contains our copy right, know-how or other proprietary. Copying without our prior permission is prohibited. 4. The specifications described in this material are subject to change without prior notice. 5. THine shall have no obligation to provide any support, installation or other assistance with regard to the information or products made in accordance with it. 6. THine, V-by-One, THine logo and V-by-One logo are trademarks or registered trademarks of THine or its subsidiaries in JAPAN and other countries.

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