当前位置:首页 >> 理学 >>

用EDA设计智力抢答器设计


一、用 EDA 设计智力抢答器设计,设计要求: 1 设计制作一个可容纳四组参赛者的数字智力抢答器,每组设置一个抢答按钮。 2 电路具有第一抢答信号鉴别和锁存功能。 3 设置记分电路。 二、原理分析: 将电路分为三个主要模块:抢答鉴别模块 QDJB;计时模块 JSQ;记分模块 JFQ;译码器显示模块 YMQ; 元件例化 QDQ 三、代码: 方法 1 用静态显示,使用 4 个数码管,两个显示计时,一个显示组别,一个显示分数 1 抢答鉴别模块 QDJB LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY QDJB IS PORT(CLR: IN STD_LOGIC; A, B, C, D: IN STD_LOGIC; --4 个组 A1,B1,C1,D1: OUT STD_LOGIC; STATES: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY QDJB; ARCHITECTURE ART OF QDJB IS signal a_1,b_1,c_1,d_1:std_logic; BEGIN PROCESS(CLR,A,B,C,D) IS BEGIN IF CLR='1' THEN STATES<="0000";a_1<='0';b_1<='0';c_1<='0';d_1<='0';--清零 elsif a_1='1' or b_1='1' or c_1='1' or d_1='1' then null;--锁存,当有一组选中时其他组再抢答没作用 elsif a='1' then a_1<='1';states<="0001"; elsif b='1' then b_1<='1';states<="0010"; elsif c='1' then c_1<='1';states<="0011"; elsif d='1' then d_1<='1';states<="0100"; end if; a1<=a_1;b1<=b_1;c1<=c_1;d1<=d_1; END PROCESS; END ARCHITECTURE ART; 2 计时模块 JSQ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JSQ IS PORT(CLR,LDN,EN,CLK: IN STD_LOGIC;

TA,TB:IN STD_LOGIC_vector(3 downto 0); QA:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --ge wei QB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --shi wei END ENTITY JSQ; ARCHITECTURE ART OF JSQ IS BEGIN PROCESS(CLK) IS VARIABLE TMPA:STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE TMPB:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF CLR='1' THEN TMPA:="0000"; TMPB:="0110"; --清零,倒计时 60 秒 ELSIF CLK'EVENT AND CLK='1' THEN IF LDN='1' THEN TMPA:=tA; TMPB:=tB; --置数控制,如果不想要 60 可以从 TA,TB 输入倒计时秒数 ELSIF EN='1' THEN--计时开始 IF TMPA="0000" THEN--遇到 9 则自动变为 0,否则减一 TMPA:="1001"; IF TMPB="0000" THEN TMPB:="0110"; ELSE TMPB:=TMPB-1; END IF; ELSE TMPA:=TMPA-1; END IF; END IF; END IF; QA<=TMPA; QB<=TMPB; END PROCESS; END ARCHITECTURE ART; 3 记分模块 JFQ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JFQ IS PORT(RST: IN STD_LOGIC; ADD: IN STD_LOGIC; CHOS: IN STD_LOGIC_VECTOR(3 DOWNTO 0); out1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY JFQ ; ARCHITECTURE ART OF JFQ IS BEGIN PROCESS(RST,ADD,CHOS) IS VARIABLE POINTS_A0: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE POINTS_B0: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE POINTS_C0: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE POINTS_D0: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN IF (ADD'EVENT AND ADD='1') THEN IF RST='1' THEN POINTS_A0:="0000"; POINTS_B0:="0000"; POINTS_C0:="0000"; POINTS_D0:="0000"; ELSIF CHOS="0001" THEN IF POINTS_A0="1001" THEN POINTS_A0:="0000"; ELSE POINTS_A0:=POINTS_A0+1; END IF; ELSIF CHOS="0010" THEN IF POINTS_B0="1001" THEN POINTS_B0:="0000"; ELSE POINTS_B0:=POINTS_B0+1; END IF; ELSIF CHOS="0011" THEN IF POINTS_C0="1001" THEN POINTS_C0:="0000"; ELSE POINTS_C0:=POINTS_C0+1; END IF; ELSIF CHOS="0100" THEN

IF POINTS_D0="1001" THEN POINTS_D0:="0000"; ELSE POINTS_D0:=POINTS_D0+1; END IF; END IF; END IF; if chos="0001" then out1<=POINTS_a0; elsif chos="0010" then out1<=POINTS_b0; elsif chos="0011" then out1<=POINTS_c0; elsif chos="0100" then out1<=POINTS_D0; elsif chos="0000" then out1<="0000"; end if; END PROCESS; END ARCHITECTURE ART; 4 译码器显示模块 YMQ

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY YMQ IS PORT(AIN4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END YMQ; ARCHITECTURE ART OF YMQ IS BEGIN PROCESS(AIN4) BEGIN CASE AIN4 IS WHEN "0000"=>DOUT7<="1111110"; WHEN "0001"=>DOUT7<="0110000"; WHEN "0010"=>DOUT7<="1101101"; WHEN "0011"=>DOUT7<="1111001"; WHEN "0100"=>DOUT7<="0110011"; WHEN "0101"=>DOUT7<="1011011"; WHEN "0110"=>DOUT7<="1011111"; WHEN "0111"=>DOUT7<="1110000"; WHEN "1000"=>DOUT7<="1111111"; WHEN "1001"=>DOUT7<="1111011"; --0 --1 --2 --3 --4 --5 --6 --7 --8 --9

WHEN OTHERS=>DOUT7<="0000000"; END CASE; END PROCESS; END ARCHITECTURE ART; 5 元件例化 library ieee; use ieee.std_logic_1164.all; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity qdq is port(qd :in std_logic_vector(3 downto 0); clk,en,ldn,add,rst,clrqd,clrsj :in std_logic; ta,tb : in std_logic_vector(3 downto 0); qdo :out std_logic_vector(3 downto 0); out1 :out std_logic_vector(3 downto 0); out2 :out std_logic_vector(3 downto 0); out4 :out std_logic_vector(3 downto 0); out3 :out std_logic_vector(3 downto 0)); end; architecture aa of qdq is component qdjb is PORT(CLR:IN STD_LOGIC;

A, B, C, D: IN STD_LOGIC; A1,B1,C1,D1: OUT STD_LOGIC; STATES: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END component QDJB; component jsq is PORT(CLR,LDN,EN,CLK: IN STD_LOGIC; TA,TB:IN STD_LOGIC_vector(3 downto 0); QA:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); QB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END component JSQ; component ymq is PORT(AIN4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END component YMQ; component jfq is PORT(RST: IN STD_LOGIC; ADD: IN STD_LOGIC; CHOS: IN STD_LOGIC_VECTOR(3 DOWNTO 0); out1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END component JFQ ; signal tmp1,tmp2,tmp3,tmp4 : std_logic_vector(3 downto 0); begin u1: qdjb port map(clr=>clrqd,a=>qd(0),b=>qd(1),c=>qd(2),d=>qd(3), a1=>qdo(0),b1=>qdo(1),c1=>qdo(2),d1=>qdo(3),STATES=>tmp1); u2: jfq port map (rst=>rst,add=>add,chos=>tmp1,out1=>out2); u3: jsq port map(clr=>clrsj,ldn=>ldn,en=>en,clk=>clk,ta=>ta,tb=>tb,qa=>out3,qb=>out4); out1<=tmp1; end;

方法 2 用动态显示

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jfq is port(rst:in std_logic; add:in std_logic; chos:in std_logic_vector(3 downto 0); PP2,PP1,PP0:OUT std_logic_vector(3 downto 0));

end entity jfq; architecture art of jfq is SIGNAL aa2,aa1,aa0,bb2,bb1,bb0: std_logic_vector(3 downto 0); SIGNAL cc2,cc1,cc0,dd2,dd1,dd0: std_logic_vector(3 downto 0); begin process(rst,add,chos) is variable points_a2,points_a1:std_logic_vector(3 downto 0); variable points_b2,points_b1:std_logic_vector(3 downto 0); variable points_c2,points_c1:std_logic_vector(3 downto 0); variable points_d2,points_d1:std_logic_vector(3 downto 0); begin IF(ADD'EVENT AND ADD='1') THEN IF RST='1'THEN POINTS_A2:="0001";POINTS_A1:="0000"; POINTS_B2:="0001";POINTS_B1:="0000"; POINTS_C2:="0001";POINTS_C1:="0000"; POINTS_D2:="0001";POINTS_D1:="0000"; ELSIF CHOS="0001"THEN IF POINTS_A1="1001"THEN POINTS_A1:="0000"; IF POINTS_A2="1001"THEN POINTS_A2:="0000"; ELSE POINTS_A2:=POINTS_A2+'1'; END IF; ELSE POINTS_A1:=POINTS_A1+'1'; AA2<=points_A2;AA1<= points_A1;AA0<="0000"; PP2<=AA2;PP1<=AA1;PP0<=AA0; END IF;

ELSIF CHOS="0010"THEN IF POINTS_B1="1001"THEN POINTS_B1:="0000"; IF POINTS_B2="1001"THEN POINTS_B2:="0000"; ELSE POINTS_B2:=POINTS_B2+'1'; END IF; ELSE POINTS_B1:=POINTS_B1+'1'; BB2<= points_B2;BB1<= points_B1;BB0<="0000"; PP2<=BB2;PP1<=BB1;PP0<=BB0; END IF; ELSIF CHOS="0100"THEN IF POINTS_C1="1001"THEN POINTS_C1:="0000"; IF POINTS_C2="1001"THEN POINTS_C2:="0000"; ELSE POINTS_C2:=POINTS_C2+'1'; CC2<= points_C2;CC1<= points_C1;CC0<="0000"; PP2<=CC2;PP1<=CC1;PP0<=CC0; END IF; ELSE POINTS_C1:=POINTS_C1+'1'; END IF; Elsif chos="1000" then If points_D1="1001" then Points_D1:="0000"; If points_D2="1001" then

Points_D2:="0000"; Else Points_D2:=points_D2+'1'; End if; Else Points_D1:=points_D1+'1'; DD2<= points_D2;DD1<= points_D1;DD0<="0000"; PP2<=DD2;PP1<=DD1;PP0<=DD0; End if; End if; End if; End process; End architecture art;

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity jsq is Port(clr,ldn,en,clk:in std_logic; TA,Tb:in std_logic; Qa:out std_logic_vector(3 downto 0); Qb:out std_logic_vector(3 downto 0)); End entity jsq; Architecture art of jsq is Signal da: std_logic_vector(3 downto 0); Signal db: std_logic_vector(3 downto 0); Begin Process(ta,tb,clr) is Begin If clr='1' then

Da<="0000"; db<="0000"; else if ta='1' then da<=da+'1'; end if; if tb='1' then db<=db+'1'; end if; end if; end process; process(clk) is variable tmpa:std_logic_vector(3 downto 0); variable tmpb:std_logic_vector(3 downto 0); begin if clr='1' then tmpa:="0000";tmpa:="0110"; elsif clk'event and clk='1' then if ldn='1' then tmpa:=da;tmpb:=db; elsif en='1' then if tmpa="0000" then tmpa:="1001"; if tmpb="0000" then tmpb:="0110"; else tmpb:=tmpb-1; end if; else tmpa:=tmpa-1; end if; end if; end if; qa<=tmpa;qb<=tmpb; end process;

end architecture art;

library ieee; use ieee.std_logic_1164.all; entity qdjb is port(clr:in std_logic; A,B,C,D:in std_logic; A1,B1,C1,D1:out std_logic; states:out std_logic_vector(3 downto 0)); end entity qdjb; architecture art of qdjb is constant w1:std_logic_vector:="0001"; constant w2:std_logic_vector:="0010"; constant w3:std_logic_vector:="0100"; constant w4:std_logic_vector:="1000"; begin process(clr,A,B,C,D) is begin if clr='1' then states<="0000"; elsif (A='1' and B='0' and C='0' and D='0') then A1<='1';B1<='0';C1<='0';D1<='0';states<=w1; elsif (A='0' and B='1' and C='0' and D='0') then A1<='0';B1<='1';C1<='0';D1<='0';states<=w2; elsif (A='0' and B='0' and C='1' and D='0') then A1<='0';B1<='0';C1<='1';D1<='0';states<=w3; elsif (A='0' and B='0' and C='0' and D='1') then A1<='0';B1<='0';C1<='0';D1<='1';states<=w4; end if; end process; end architecture art;

library ieee; use ieee.std_logic_1164.all; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity qdq is port(qd :in std_logic_vector(3 downto 0); ck,clk,en,ldn,add,rst,clr:in std_logic; TA,TB:in std_logic; qdo :out std_logic_vector(3 downto 0); sel:out std_logic_vector(5 downto 0); sm:out std_logic_vector(6 downto 0)); end; architecture aa of qdq is component qdjb is PORT(CLR: IN STD_LOGIC; A, B, C, D: IN STD_LOGIC; A1,B1,C1,D1: OUT STD_LOGIC; STATES: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END component QDJB; component jsq is PORT(CLR,LDN,EN,CLK: IN STD_LOGIC; TA,TB:IN STD_LOGIC; QA:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); QB :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END component JSQ; component jfq is PORT(RST: IN STD_LOGIC; ADD: IN STD_LOGIC; CHOS: IN STD_LOGIC_VECTOR(3 DOWNTO 0); pp2,pp1,pp0:inOUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END component JFQ ; signal tmp1,tmp2,tmp3: std_logic_vector(3 downto 0); signal pp22,pp11,pp00: std_logic_vector(3 downto 0); signal tmp: integer range 0 to 5; signal q_s:std_logic_vector(3 downto 0); begin u1:qdjb port map(clr,qd(0),qd(1),qd(2),qd(3), qdo(0),qdo(1),qdo(2),qdo(3),tmp1); u2: jfq port map (rst,add,tmp1,pp22,pp11,pp00); u3: jsq port map(clr,ldn,en,clk,ta,tb,tmp2,tmp3); process(ck) is begin if (ck'event and ck='1') then tmp<=tmp+1; end if; end process; process(tmp) is begin if tmp=0 then q_s<=tmp1; sel<="000001"; elsif tmp=1 then q_s<=tmp2; sel<="000010"; elsif tmp=2 then q_s<=tmp3; sel<="000100"; elsif tmp=3 then q_s<=pp00; sel<="001000"; elsif tmp=4 then q_s<=pp11; sel<="010000"; else q_s<=pp22; sel<="100000";

end if; end process; process(q_s) is begin case q_s is when"0000"=>sm<="0111111"; when"0001"=>sm<="0000110"; when"0010"=>sm<="1011011"; when"0011"=>sm<="1001111"; when"0100"=>sm<="1100110"; when"0101"=>sm<="1101101";when"0110"=>sm<="1111101";when"0111" =>sm<="0000111"; when"1000"=>sm<="1111111"; when"1001"=>sm<="1101111"; when others=>sm<="0000000"; end case;end process;end;


相关文章:
数电EDA课程设计智力竞赛抢答器
数电EDA课程设计智力竞赛抢答器_电子/电路_工程科技_专业资料。燕山大学 EDA 课程...初步掌握了其应用软件 MAX-Plus 的使用, 而且更为深入的体会了数字电路在现代...
用EDA设计智力抢答器设计
用EDA设计智力抢答器设计用EDA设计智力抢答器设计隐藏>> 一、用 EDA 设计智力抢答器设计,设计要求: 1 设计制作一个可容纳四组参赛者的数字智力抢答器,每组设置一...
EDA课程设计四路智能抢答器
EDA课程设计四路智能抢答器 隐藏>> 一、课题简介在许多比赛活动中,为了准确、公正、直观地判断出第一抢答者,通常设置 一台抢答器,通过数显、灯光及音响等各种手段...
EDA-智力抢答器的设计与分析
EDA-智力抢答器设计与分析_工学_高等教育_教育专区。摘要 EDA 技术作为现代电子设计最新技术的结晶,其广阔的应用前景和深远的影响 已毋庸置疑,它在信息工程类...
基于EDA的智力抢答器的课程设计说明书
基于EDA智力抢答器的课程设计说明书_工学_高等教育_教育专区 暂无评价|0人阅读|0次下载基于EDA智力抢答器的课程设计说明书_工学_高等教育_教育专区。山东建筑...
EDA课程设计智力抢答器
EDA课程设计智力抢答器 隐藏>> 一、设计题目: 智力竞赛抢答器 设计题目: 设计题目 电路功能: 二、电路功能 个组,同时参加竞赛。抢答器复位后, 可满足 8 个组...
EDA课程设计抢答器
EDA课程设计EDA课程设计隐藏>> 内容摘要抢答器是为智力竞赛参赛者答题时进行抢答而设计的一种优先 判决器电路,竞赛者可以分为若干组,抢答时各组对主持人提出的问 ...
基于EDA的智力抢答器的课程设计说明书
基于EDA智力抢答器的课程设计说明书_工学_高等教育_教育专区 暂无评价|0人阅读|0次下载基于EDA智力抢答器的课程设计说明书_工学_高等教育_教育专区。山东建筑...
基于EDA的智力抢答器的课程设计说明书1 精品
基于EDA智力抢答器的课程设计说明书1 精品_工学_高等教育_教育专区 暂无评价|0人阅读|0次下载基于EDA智力抢答器的课程设计说明书1 精品_工学_高等教育_教育...
EDA智力竞赛抢答器设计
EDA 智力竞赛抢答器设计一、实训目的: 1、了解竞赛抢答器的工作原理; 2、熟悉 VHDL 语言编程,了解实际设计中的优化方案。 二、实训内容: 设计一个数字式竞赛抢答...
更多相关标签: