当前位置:首页 >> 电子/电路 >>

MX25L25635F,


MX25L25635F

MX25L25635F
3V, 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO? (SERIAL MULTI I/O) FLASH MEMORY

P/N: PM1738

MX25L25635F

Contents
1. FEATURES............................................................................................................................................................... 4 2. GENERAL DESCRIPTION...................................................................................................................................... 6 Table 1. Read performance Comparison.....................................................................................................6 3. PIN CONFIGURATIONS .......................................................................................................................................... 7 4. PIN DESCRIPTION................................................................................................................................................... 7 5. BLOCK DIAGRAM.................................................................................................................................................... 8 6. DATA PROTECTION................................................................................................................................................. 9 Table 2. Protected Area Sizes....................................................................................................................10 Table 3. 4K-bit Secured OTP Definition..................................................................................................... 11 7. Memory Organization............................................................................................................................................ 12 Table 4. Memory Organization...................................................................................................................12 8. DEVICE OPERATION............................................................................................................................................. 13 8-1. 256Mb Address Protocol........................................................................................................................... 15 8-2. Quad Peripheral Interface (QPI) Read Mode........................................................................................... 16 9. COMMAND DESCRIPTION.................................................................................................................................... 17 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 9-7. 9-8. 9-9. 9-10. 9-11. 9-12. 9-13. 9-14. 9-15. 9-16. 9-17. 9-18. 9-19. 9-20. 9-21. 9-22. 9-23. 9-24.
P/N: PM1738

Table 5. Command Set...............................................................................................................................17 Write Enable (WREN)............................................................................................................................... 22 Write Disable (WRDI)................................................................................................................................ 23 Read Identification (RDID)........................................................................................................................ 24 Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................ 25 Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 27 QPI ID Read (QPIID)................................................................................................................................ 28 Table 6. ID Definitions ...............................................................................................................................28 Read Status Register (RDSR).................................................................................................................. 29 Read Configuration Register (RDCR)....................................................................................................... 30 Table 7. Configuration Register..................................................................................................................34 Write Status Register (WRSR).................................................................................................................. 36 Table 8. Protection Modes..........................................................................................................................37 Enter 4-byte mode (EN4B)....................................................................................................................... 40 Exit 4-byte mode (EX4B).......................................................................................................................... 40 Read Data Bytes (READ)......................................................................................................................... 41 Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 42 Dual Output Read Mode (DREAD)........................................................................................................... 44 2 x I/O Read Mode (2READ).................................................................................................................... 45 Quad Read Mode (QREAD)..................................................................................................................... 46 4 x I/O Read Mode (4READ).................................................................................................................... 47 4 Byte Address Command Set.................................................................................................................. 49 Burst Read................................................................................................................................................ 51 Performance Enhance Mode.................................................................................................................... 52 Fast Boot.................................................................................................................................................. 55 Sector Erase (SE)..................................................................................................................................... 58 Block Erase (BE32K)................................................................................................................................ 59 Block Erase (BE)...................................................................................................................................... 60
2
Rev. 1.5, September 26, 2016

MX25L25635F
Chip Erase (CE)........................................................................................................................................ 61 Page Program (PP).................................................................................................................................. 62 4 x I/O Page Program (4PP)..................................................................................................................... 64 Deep Power-down (DP)............................................................................................................................ 65 Enter Secured OTP (ENSO)..................................................................................................................... 66 Exit Secured OTP (EXSO)........................................................................................................................ 66 Read Security Register (RDSCUR).......................................................................................................... 66 Write Security Register (WRSCUR).......................................................................................................... 66 Table 9. Security Register Definition..........................................................................................................67 9-33. Write Protection Selection (WPSEL)......................................................................................................... 68 9-34. Advanced Sector Protection..................................................................................................................... 70 9-35. Program/Erase Suspend/Resume............................................................................................................ 78 9-36. Erase Suspend......................................................................................................................................... 78 9-37. Program Suspend..................................................................................................................................... 78 9-38. Write-Resume........................................................................................................................................... 80 9-39. No Operation (NOP)................................................................................................................................. 80 9-40. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 80 9-41. Read SFDP Mode (RDSFDP)................................................................................................................... 82 Table 10. Signature and Parameter Identification Data Values .................................................................83 Table 11. Parameter Table (0): JEDEC Flash Parameter Tables...............................................................84 Table 12. Parameter Table (1): Macronix Flash Parameter Tables............................................................86 10. RESET.................................................................................................................................................................. 88 Table 13. Reset Timing-(Power On)...........................................................................................................88 Table 14. Reset Timing-(Other Operation).................................................................................................88 11. POWER-ON STATE.............................................................................................................................................. 89 12. ELECTRICAL SPECIFICATIONS......................................................................................................................... 90 Table 15. ABSOLUTE MAXIMUM RATINGS.............................................................................................90 Table 16. CAPACITANCE TA = 25°C, f = 1.0 MHz.....................................................................................90 Table 17. DC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V) ........................92 Table 18. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V) .......................93 13. OPERATING CONDITIONS.................................................................................................................................. 94 Table 19. Power-Up/Down Voltage and Timing .........................................................................................96 13-1. INITIAL DELIVERY STATE....................................................................................................................... 96 14. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 97 15. DATA RETENTION............................................................................................................................................... 97 16. LATCH-UP CHARACTERISTICS......................................................................................................................... 97 17. ORDERING INFORMATION................................................................................................................................. 98 18. PART NAME DESCRIPTION................................................................................................................................ 99 19. PACKAGE INFORMATION................................................................................................................................. 100 20. REVISION HISTORY .......................................................................................................................................... 102 9-25. 9-26. 9-27. 9-28. 9-29. 9-30. 9-31. 9-32.

P/N: PM1738

3

Rev. 1.5, September 26, 2016

MX25L25635F
3V 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO? (SERIAL MULTI I/O) FLASH MEMORY 1. FEATURES
GENERAL ? Supports Serial Peripheral Interface -- Mode 0 and Mode 3 ? Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations ? 256Mb: 268,435,456 x 1 bit structure or 134,217,728 x 2 bits (two I/O mode) structure or 67,108,864 x 4 bits (four I/O mode) structure ? Protocol Support - Single I/O, Dual I/O and Quad I/O ? Latch-up protected to 100mA from -1V to Vcc +1V ? Fast read for SPI mode - Support clock frequency up to 133MHz for all protocols - Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions. - Configurable dummy cycle number for fast read operation ? Quad Peripheral Interface (QPI) available ? Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually ? Programming : - 256byte page buffer - Quad Input/Output page program(4PP) to enhance program performance ? Typical 100,000 erase/program cycles ? 20 years data retention SOFTWARE FEATURES ? Input Data Format - 1-byte Command code ? Advanced Security Features - Block lock protection The BP0-BP3 and T/B status bits define the size of the area to be protected against program and erase instructions - Advanced sector protection function (Solid and Password Protect) ? Additional 4K bit security OTP - Features unique identifier - Factory locked identifiable, and customer lockable ? Command Reset ? Program/Erase Suspend and Resume operation ? Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID ? Support Serial Flash Discoverable Parameters (SFDP) mode

P/N: PM1738

4

Rev. 1.5, September 26, 2016

MX25L25635F
HARDWARE FEATURES ? SCLK Input - Serial clock input ? SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode ? SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode ? WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode ? RESET#/SIO3 - Hardware Reset pin or Serial input & Output for 4 x I/O read mode ? PACKAGE - 16-pin SOP (300mil) - 8-land WSON (8x6mm) - All devices are RoHS Compliant and Halogen-free

P/N: PM1738

5

Rev. 1.5, September 26, 2016

MX25L25635F
2. GENERAL DESCRIPTION
MX25L25635F is 256Mb bits serial Flash memory, which is configured as 33,554,432 x 8 internally. When it is in two or four I/O mode, the structure becomes 134,217,728 bits x 2 or 67,108,864 bits x 4. MX25L25635F feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25L25635F MXSMIO? (Serial Multi I/O) provides sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte), or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode. The MX25L25635F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.

Table 1. Read performance Comparison Numbers of Dummy Cycles 4 6 8 10 Fast Read (MHz) 104 104* 133 Dual Output Fast Read (MHz) 104 104* 133 Quad Output Fast Read (MHz) 84 104* 133 Dual IO Fast Read (MHz) 84* 104 104 133 Quad IO Fast Read (MHz) 70 84* 104 133

Note: * mean default status

P/N: PM1738

6

Rev. 1.5, September 26, 2016

MX25L25635F
3. PIN CONFIGURATIONS
16-PIN SOP (300mil)
DNU/SIO3 VCC RESET# NC NC NC CS# SO/SIO1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SCLK SI/SIO0 NC NC NC NC GND WP#/SIO2

4. PIN DESCRIPTION
DESCRIPTION Chip Select Serial Data Input (for 1 x I/O)/ Serial SI/SIO0 Data Input & Output (for 2xI/O or 4xI/ O read mode) Serial Data Output (for 1 x I/O)/ Serial SO/SIO1 Data Input & Output (for 2xI/O or 4xI/ O read mode) SCLK Clock Input Write protection Active low or Serial WP#/SIO2 Data Input & Output (for 4xI/O read mode) Hardware Reset Pin Active low or RESET#/SIO3 Serial Data Input & Output (for 4xI/O read mode) Do not use or Serial Data Input & DNU/SIO3 Output (for 4xI/O read mode) RESET#* Hardware Reset Pin Active low VCC + 3V Power Supply GND Ground NC No Connection Notes: 1. RESET# pin has internal pull up. 2. When using 1I/O or 2I/O (QE bit not enable), the DNU/SIO3 pin of 16SOP can not connect to GND. Recommend to connect this pin to VCC or floating. SYMBOL CS#

8-WSON (8x6mm)
CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 8 7 6 5 VCC RESET#/SIO3 SCLK SI/SIO0

P/N: PM1738

7

Rev. 1.5, September 26, 2016

MX25L25635F
5. BLOCK DIAGRAM
Address Generator

X-Decoder

Memory Array

Page Buffer Data Register Y-Decoder SRAM Buffer CS# WP#/SIO2 RESET#/SIO3 Mode Logic State Machine Sense Amplifier
HV Generator

SI/SIO0

SCLK SO/SIO1

Clock Generator Output Buffer

P/N: PM1738

8

Rev. 1.5, September 26, 2016

MX25L25635F
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. ? Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. ? Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. ? Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES), and softreset command. ? Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be protected as read only. The protected area definition is shown as Table 2 Protected Area Sizes, the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. - The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Register Write Protect bit. - In four I/O and QPI mode, the feature of HPM will be disabled.



P/N: PM1738

9

Rev. 1.5, September 26, 2016

MX25L25635F
Table 2. Protected Area Sizes Protected Area Sizes (T/B bit = 0) Status bit BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Protect Level 256Mb 0 (none) 1 (1 block, protected block 511th) 2 (2 blocks, protected block 510th~511th) 3 (4 blocks, protected block 508th~511th) 4 (8 blocks, protected block 504th~511th) 5 (16 blocks, protected block 496th~511th) 6 (32 blocks, protected block 480th~511th) 7 (64 blocks, protected block 448th~511th) 8 (128 blocks, protected block 384th~511th) 9 (256 blocks, protected block 256th~511th) 10 (512 blocks, protected all) 11 (512 blocks, protected all) 12 (512 blocks, protected all) 13 (512 blocks, protected all) 14 (512 blocks, protected all) 15 (512 blocks, protected all)

Protected Area Sizes (T/B bit = 1) Status bit BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Protect Level 256Mb 0 (none) 1 (1 block, protected block 0th) 2 (2 blocks, protected block 0th~1st) 3 (4 blocks, protected block 0th~3rd) 4 (8 blocks, protected block 0th~7th) 5 (16 blocks, protected block 0th~15th) 6 (32 blocks, protected block 0th~31st) 7 (64 blocks, protected block 0th~63rd) 8 (128 blocks, protected block 0th~127th) 9 (256 blocks, protected block 0th~255th) 10 (512 blocks, protected all) 11 (512 blocks, protected all) 12 (512 blocks, protected all) 13 (512 blocks, protected all) 14 (512 blocks, protected all) 15 (512 blocks, protected all)

P/N: PM1738

10

Rev. 1.5, September 26, 2016

MX25L25635F
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting device unique serial number - Which may be set by factory or system customer. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter Security OTP command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing Exit Security OTP command.

- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to "Table 9. Security Register Definition" for security register bit definition and "Table 3. 4K-bit Secured OTP Definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured OTP mode, array access is not allowed.

Table 3. 4K-bit Secured OTP Definition Address range xxx000~xxx00F xxx010~xxx1FF Size 128-bit 3968-bit Standard Factory Lock ESN (electrical serial number) N/A Customer Lock Determined by customer

P/N: PM1738

11

Rev. 1.5, September 26, 2016

MX25L25635F
7. Memory Organization
Table 4. Memory Organization
Block(64K-byte) Block(32K-byte) 1023 511 1022 Sector 8191 … 8184 8183 … 8176 8175 … 1021 510 1020 individual block lock/unlock unit:64K-byte 1019 509 1018 8168 8167 … 8160 8159 … 8152 8151 … 8144 Address Range 1FFF000h … 1FF8000h 1FF7000h … 1FF0000h 1FEF000h … 1FE8000h 1FE7000h … 1FE0000h 1FDF000h … 1FD8000h 1FD7000h … 1FD0000h 1FFFFFFh … 1FF8FFFh 1FF7FFFh 1FF0FFFh 1FEFFFFh 1FE8FFFh 1FE7FFFh 1FE0FFFh 1FDFFFFh 1FD8FFFh 1FD7FFFh 1FD0FFFh … … … … … individual 16 sectors lock/unlock unit:4K-byte

individual block lock/unlock unit:64K-byte

47 5 2 individual block lock/unlock unit:64K-byte 4 … 40 39 … 32 31 … 3 1 2 24 23 … 16 15 … 1 0 0 8 7 … 0
P/N: PM1738

002F000h … 0028000h 027000h … 0020000h 001F000h … 0018000h 0017000h … 0010000h 000F000h … 0008000h 0007000h … 0000000h

002FFFFh 0028FFFh 0027FFFh 0020FFFh 001FFFFh 0018FFFh 0017FFFh 0010FFFh 000FFFFh … 0008FFFh 0007FFFh 0000FFFh
Rev. 1.5, September 26, 2016









individual 16 sectors lock/unlock unit:4K-byte

12



MX25L25635F
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z. 3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Serial Modes Supported". 5. For the following instructions: RDID, RDSR, RDSCUR, READ/READ4B, FAST_READ/FAST_READ4B, 2READ/2READ4B, DREAD/DREAD4B, 4READ/4READ4B, QREAD/QREAD4B, RDSFDP, RES, REMS, QPIID, RDDPB, RDSPB, RDPASS, RDLR, RDEAR, RDFBR, RDSPBLK, RDCR, the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, PP/PP4B, 4PP/4PP4B, DP, ENSO, EXSO, WRSCUR, EN4B, EX4B, WPSEL, GBLK, GBULK, SPBLK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported
CPOL (Serial mode 0) 0 CPHA 0 SCLK shift in shift out

(Serial mode 3)

1

1

SCLK

SI

MSB

SO

MSB

Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported.

P/N: PM1738

13

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 2. Serial Input Timing
tSHSL CS# tCHSL SCLK tDVCH tCHDX SI MSB tCLCH LSB tCHCL tSLCH tCHSH tSHCH

SO

High-Z

Figure 3. Output Timing

CS# tCH SCLK tCLQV tCLQX SO tCLQX LSB tCLQV tCL tSHQZ

SI

ADDR.LSB IN

P/N: PM1738

14

Rev. 1.5, September 26, 2016

MX25L25635F
8-1. 256Mb Address Protocol The original 24 bit address protocol of serial Flash can only access density size below 128Mb. For the memory device of 256Mb and above, the 32bit address is requested for access higher memory size. The MX25L25635F provides three different methods to access the whole 256Mb density: (1)Command entry 4-byte address mode: Issue Enter 4-Byte mode command to set up the 4BYTE bit in Configuration Register bit. After 4BYTE bit has been set, the number of address cycle become 32-bit. (2)Extended Address Register (EAR): configure the memory device into two 128Mb segments to select which one is active through the EAR bit “0”. (3)4-byte Address Command Set: When issuing 4-byte address command set, 4-byte address (A31-A0) is requested after the instruction code. Please note that it is not necessary to issue EN4B command before issuing any of 4-byte command set. Enter 4-Byte Address Mode In 4-byte Address mode, all instructions are 32-bits address clock cycles. By using EN4B and EX4B to enable and disable the 4-byte address mode. When 4-byte address mode is enabled, the EAR<0> becomes "don't care" for all instructions requiring 4-byte address. The EAR function will be disabled when 4-byte mode is enabled. Extended Address Register (Configurable) The device provides an 8-bit volatile register for extended Address Register: it identifies the extended address (A31~A24) above 128Mb density by using original 3-byte address. Extended Address Register (EAR) Bit 7 A31 Bit 6 A30 Bit 5 A29 Bit 4 A28 Bit 3 A27 Bit 2 A26 Bit 1 A25 Bit 0 A24

For the MX25L25635F the A31 to A25 are Don't Care. During EAR, reading these bits will read as 0. The bit 0 is default as "0". Figure 4. Top and Bottom 128M bits
Top 128Mb 01FFFFFFh 01000000h Bottom 128Mb 00FFFFFFh 00000000h EAR<0>= 0 (default) EAR<0>= 1

When under EAR mode, Read, Program, Erase operates in the selected segment by using 3-byte address mode. For the read operation, the whole array data can be continually read out with one command. Data output starts from the selected top or bottom 128Mb, but it can cross the boundary. When the last byte of the segment is reached, the next byte (in a continuous reading) is the first byte of the next segment. However, the EAR (Extended Address Register) value does not change. The random access reading can only be operated in the selected segment. The Chip erase command will erase the whole chip and is not limited by EAR selected segment.
P/N: PM1738

15

Rev. 1.5, September 26, 2016

MX25L25635F
8-2. Quad Peripheral Interface (QPI) Read Mode QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in command cycles, address cycles and as well as data output cycles. Enable QPI mode By issuing 35H command, the QPI mode is enabled. After QPI mode is enabled, the device enters quad mode (4-4-4) without QE bit status changed. Figure 5. Enable QPI Sequence
CS#
MODE 3 0 1 2 3 4 5 6 7

SCLK SIO0 SIO[3:1]

MODE 0

35h

Reset QPI (RSTQIO) To reset the QPI mode, the RSTQIO (F5H) command is required. After the RSTQIO command is issued, the device returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles). Note: For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL for next instruction.

Figure 6. Reset QPI Mode
CS# SCLK SIO[3:0] F5h

P/N: PM1738

16

Rev. 1.5, September 26, 2016

MX25L25635F
9. COMMAND DESCRIPTION
Table 5. Command Set Read/Write Array Commands
Command (byte) Mode
Address Bytes

READ FAST READ (normal read) (fast read data) SPI 3/4 03 (hex) ADD1 ADD2 ADD3 SPI 3/4 0B (hex) ADD1 ADD2 ADD3 Dummy* n bytes read out until CS# goes high n bytes read out until CS# goes high

(2 x I/O read command)

2READ

DREAD (1I 2O read) SPI 3/4 3B (hex) ADD1 ADD2 ADD3 Dummy*

(4 I/O read start (4 I/O read start from bottom from Top 128Mb) 128Mb)

4READ

4READ

QREAD (1I 4O read) SPI 3/4 6B (hex) ADD1 ADD2 ADD3 Dummy*

1st byte 2nd byte 3rd byte 4th byte 5th byte

SPI 3/4 BB (hex) ADD1 ADD2 ADD3 Dummy*

SPI/QPI 3/4 EB (hex) ADD1 ADD2 ADD3 Dummy*

SPI/QPI 3/4 EA (hex) ADD1 ADD2 ADD3 Dummy*

Data Cycles
Action n bytes read n bytes read Quad I/O read Quad I/O read n bytes read out by 2 x I/O out by Dual for bottom for Top 128Mb out by Quad until CS# goes output until 128Mb with 6 with 6 dummy output until high CS# goes high dummy cycles cycles CS# goes high BE 32K (block erase 32KB) SPI/QPI 3/4 52 (hex) ADD1 ADD2 ADD3 BE (block erase 64KB) SPI/QPI 3/4 D8 (hex) ADD1 ADD2 ADD3

Command (byte) Mode
Address Bytes

PP (page program) SPI/QPI 3/4 02 (hex)

4PP (quad page program) SPI 3/4 38 (hex) ADD1 ADD2 ADD3

SE (sector erase) SPI/QPI 3/4 20 (hex) ADD1 ADD2 ADD3

CE (chip erase) SPI/QPI 0 60 or C7 (hex)

1st byte 2nd byte 3rd byte 4th byte 5th byte

Data Cycles
Action

1-256 to program the selected page

1-256 quad input to to erase the to erase the program the selected sector selected 32K selected page block

to erase the to erase whole selected block chip

* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register.

P/N: PM1738

17

Rev. 1.5, September 26, 2016

MX25L25635F
Read/Write Array Commands (4 Byte Address Command Set)
Command (byte) Mode
Address Bytes

READ4B SPI 4 13 (hex) ADD1 ADD2 ADD3 ADD4

FAST READ4B SPI 4 0C (hex) ADD1 ADD2 ADD3 ADD4 Dummy

2READ4B SPI 4 BC (hex) ADD1 ADD2 ADD3 ADD4 Dummy

DREAD4B SPI 4 3C (hex) ADD1 ADD2 ADD3 ADD4 Dummy

4READ4B SPI/QPI 4 EC (hex) ADD1 ADD2 ADD3 ADD4 Dummy

QREAD4B SPI 4 6C (hex) ADD1 ADD2 ADD3 ADD4 Dummy

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte

Data Cycles
Action read data byte by read data byte by read data byte by Read data byte by read data byte by Read data byte by 4 byte address 4 byte address 2 x I/O with 4 byte Dual Output with 4 x I/O with 4 byte Quad Output with address 4 byte address address 4 byte address PP4B SPI/QPI 4 12 (hex) ADD1 ADD2 ADD3 ADD4 1-256 to program the selected page with 4byte address 4PP4B SPI 4 3E (hex) ADD1 ADD2 ADD3 ADD4 1-256 Quad input to program the selected page with 4byte address BE4B (block erase 64KB) SPI/QPI 4 DC (hex) ADD1 ADD2 ADD3 ADD4 BE32K4B (block erase 32KB) SPI/QPI 4 5C (hex) ADD1 ADD2 ADD3 ADD4 SE4B (Sector erase 4KB) SPI/QPI 4 21 (hex) ADD1 ADD2 ADD3 ADD4

Command (byte) Mode
Address Bytes

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte Data Cycles

Action

to erase the selected (64KB) block with 4byte address

to erase the to erase the selected (32KB) selected (4KB) block with 4byte sector with 4byte address address

P/N: PM1738

18

Rev. 1.5, September 26, 2016

MX25L25635F
Register/Setting Commands
Command (byte) Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte Data Cycles sets the (WEL) resets the to read out the to read out the write enable (WEL) write values of the values of the latch bit enable latch bit status register configuration register 1-2 to write new values of the status/ configuration register EX4B (exit 4-byte mode) SPI/QPI E9 (hex) 1 read extended write extended address address register register WREN WRDI (write enable) (write disable) SPI/QPI 06 (hex) SPI/QPI 04 (hex) RDSR (read status register) SPI/QPI 05 (hex) RDCR (read configuration register) SPI/QPI 15 (hex) WRSR RDEAR WREAR (write status/ (read extended (write extended configuration address address register) register) register) SPI/QPI SPI/QPI SPI/QPI 01 (hex) Values Values C8 (hex) C5 (hex)

Action

Command (byte) Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte Data Cycles Action

WPSEL (Write Protect Selection) SPI/QPI 68 (hex)

EQIO (Enable QPI) SPI 35 (hex)

RSTQIO (Reset QPI) QPI F5 (hex)

EN4B (enter 4-byte mode) SPI/QPI B7 (hex)

PGM/ERS Suspend (Suspends Program/ Erase) SPI/QPI B0 (hex)

PGM/ERS Resume (Resumes Program/ Erase) SPI/QPI 30 (hex)

to enter and enable individal block protect mode

Entering the QPI mode

Exiting the QPI to enter 4-byte to exit 4-byte mode mode and set mode and clear 4BYTE bit as 4BYTE bit to "1" be "0" SBL (Set Burst Length) SPI/QPI C0 (hex) RDFBR WRFBR ESFBR (read fast boot (write fast boot (erase fast register) register) boot register) SPI SPI SPI 16(hex) 17(hex) 18(hex)

Command (byte) Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte Data Cycles Action

DP (Deep power down) SPI/QPI B9 (hex)

RDP (Release from deep power down) SPI/QPI AB (hex)

1-4 enters deep power down mode release from deep power down mode to set Burst length

4

P/N: PM1738

19

Rev. 1.5, September 26, 2016

MX25L25635F
ID/Security Commands
Command (byte) Mode
Address Bytes

1st byte 2nd byte 3rd byte 4th byte 5th byte

REMS RDID RES (read electronic QPIID (read identific- (read electronic manufacturer & (QPI ID Read) ation) ID) device ID) SPI SPI/QPI SPI QPI 0 0 0 0 9F (hex) AB (hex) 90 (hex) AF (hex) x x x x ADD1 (Note 1) outputs JEDEC to read out output the ID: 1-byte 1-byte Device Manufacturer Manufacturer ID ID & Device ID ID & 2-byte Device ID RDSCUR (read security register) SPI/QPI 0 2B (hex) WRSCUR (write security register) SPI/QPI 0 2F (hex) GBLK (gang block lock) SPI/QPI 0 7E (hex) ID in QPI interface

RDSFDP SPI/QPI 3 5A (hex) ADD1 ADD2 ADD3 Dummy (8) Read SFDP mode

ENSO (enter secured OTP) SPI/QPI 0 B1 (hex)

EXSO (exit secured OTP) SPI/QPI 0 C1 (hex)

Action

to enter the to exit the 4K-bit secured 4K-bit secured OTP mode OTP mode

Command (byte) Mode
Address Bytes

GBULK (gang block unlock) SPI/QPI 0 98 (hex)

WRLR (write Lock register) SPI 0 2C (hex)

RDLR (read Lock register) SPI 0 2D (hex)

WRPASS (write password register) SPI 0 28 (hex)

RDPASS (read password register) SPI 0 27 (hex)

1st byte 2nd byte 3rd byte 4th byte 5th byte Data Cycles

2 whole chip to read value to set the of security lock-down bit write protect register as "1" (once lock-down, cannot be updated) PASSULK (password unlock) SPI 0 29 (hex) WRSPB (SPB bit program) SPI 4 E3 (hex) ADD1 ADD2 ADD3 ADD4 8 ESSPB (all SPB bit erase) SPI 0 E4 (hex) whole chip unprotect

2

1-8

1-8

Action

Command (byte) Mode
Address Bytes

RDSPB (read SPB status) SPI 4 E2 (hex) ADD1 ADD2 ADD3 ADD4 1

SPBLK (SPB lock set) SPI 0 A6 (hex)

RDSPBLK WRDPB (SPB lock (write DPB register read) register) SPI SPI 0 4 A7 (hex) E1 (hex) ADD1 ADD2 ADD3 ADD4 2 1

RDDPB (read DPB register) SPI 4 E0 (hex) ADD1 ADD2 ADD3 ADD4 1

1st byte 2nd byte 3rd byte 4th byte 5th byte Data Cycles Action

P/N: PM1738

20

Rev. 1.5, September 26, 2016

MX25L25635F
Reset Commands
Command (byte) Mode 1st byte 2nd byte 3rd byte 4th byte 5th byte NOP RSTEN (No Operation) (Reset Enable) SPI/QPI 00 (hex) SPI/QPI 66 (hex) RST (Reset Memory) SPI/QPI 99 (hex)

Action

Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SO/SIO1 which is different from 1 x I/O condition. Note 2: ADD=00H will output the manufacturer ID first and AD=01H will output device ID first. Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 4: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the reset operation will be disabled. Note 5: The number in parentheses after "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)" represents there are 8 clock cycles for the data in. Please note the number after "ADD" are based on 3-byte address mode, for 4-byte address mode, which will be increased.

P/N: PM1738

21

Rev. 1.5, September 26, 2016

MX25L25635F
9-1. Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP/ PP4B, 4PP/4PP4B, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, and WRSR, which are intended to change the device content WEL bit should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in SPI mode. Figure 7. Write Enable (WREN) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 SI Command 06h High-Z 0 1 2 3 4 5 6 7

SO

Figure 8. Write Enable (WREN) Sequence (QPI Mode)
CS#
Mode 3

0

1

SCLK
Mode 0 Command

SIO[3:0]

06h

P/N: PM1738

22

Rev. 1.5, September 26, 2016

MX25L25635F
9-2. Write Disable (WRDI) The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in SPI mode. The WEL bit is reset by following situations: - Power-up - Reset# pin driven low - WRDI command completion - WRSR command completion - PP/PP4B command completion - 4PP/4PP4B command completion - SE/SE4B command completion - BE32K/BE32K4B command completion - BE/BE4B command completion - CE command completion - PGM/ERS Suspend command completion - Softreset command completion - WRSCUR command completion - WPSEL command completion - GBLK command completion - GBULK command completion - WREAR command completion - WRLR command completion - WRPASS command completion - SPBLK command completion - WRSPB command completion - ESSPB command completion - WRDPB command completion - WRFBR command completion - ESFBR command completion

Figure 9. Write Disable (WRDI) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 SI Command 04h High-Z 0 1 2 3 4 5 6 7

SO

P/N: PM1738

23

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 10. Write Disable (WRDI) Sequence (QPI Mode)

CS#
Mode 3

0

1

SCLK
Mode 0 Command

SIO[3:0]

04h

9-3. Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as Table 6 ID Definitions. The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID operation can drive CS# to high at any time during data out. While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.

Figure 11. Read Identification (RDID) Sequence (SPI mode only)

CS# Mode 3 SCLK Mode 0 SI Command 9Fh Manufacturer Identification SO High-Z 7 MSB 6 5 2 1 Device Identification 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 28 29 30 31

0 15 14 13 MSB

P/N: PM1738

24

Rev. 1.5, September 26, 2016

MX25L25635F
9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 18 AC Characteristics. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only for releasing from Deep Power Down Mode. Reset# pin goes low will release the Flash from deep power down mode. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as Table 6 ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction.

Figure 12. Read Electronic Signature (RES) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 Command 3 Dummy Bytes tRES2 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38

SI High-Z

ABh

23 22 21 MSB

3

2

1

0 Electronic Signature Out 7 MSB Deep Power-down Mode Stand-by Mode 6 5 4 3 2 1 0

SO

P/N: PM1738

25

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 13. Read Electronic Signature (RES) Sequence (QPI Mode)
CS#
MODE 3

0

1

2

3

4

5

6

7

SCLK
MODE 0
Command 3 Dummy Bytes

SIO[3:0]

ABh
Data In

X

X

X

X

X

X

H0

L0

MSB LSB Data Out

Deep Power-down Mode

Stand-by Mode

Figure 14. Release from Deep Power-down (RDP) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 SI Command ABh High-Z 0 1 2 3 4 5 6 7 tRES1

SO

Deep Power-down Mode

Stand-by Mode

Figure 15. Release from Deep Power-down (RDP) Sequence (QPI Mode)

CS#
Mode 3

tRES1
0 1

SCLK
Mode 0 Command

SIO[3:0]

ABh

Deep Power-down Mode

Stand-by Mode

P/N: PM1738

26

Rev. 1.5, September 26, 2016

MX25L25635F
9-5. Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first. The Device ID values are listed in Table 6 of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.

Figure 16. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)

CS# Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10

SCLK

Command

2 Dummy Bytes

SI

90h High-Z

15 14 13

3

2

1

0

SO

CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1)

SI

7

6

5

4

3

2

1

0 Manufacturer ID Device ID 0 7 MSB 6 5 4 3 2 1 0 7 MSB

SO

7 MSB

6

5

4

3

2

1

Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.

P/N: PM1738

27

Rev. 1.5, September 26, 2016

MX25L25635F
9-6. QPI ID Read (QPIID) User can execute this QPIID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes high. Most significant bit (MSB) first. After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID, memory type, and device ID data byte will be output continuously, until the CS# goes high.

Table 6. ID Definitions Command Type RDID RES REMS QPIID 9Fh ABh 90h AFh Manufactory ID C2 Manufactory ID C2 Manufactory ID C2 MX25L25635F Memory type 20 Electronic ID 18 Device ID 18 Memory type 20 Memory density 19

Memory density 19

P/N: PM1738

28

Rev. 1.5, September 26, 2016

MX25L25635F
9-7. Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode.

Figure 17. Read Status Register (RDSR) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 SI High-Z command 05h Status Register Out 7 MSB 6 5 4 3 2 1 0 7 MSB Status Register Out 6 5 4 3 2 1 0 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SO

Figure 18. Read Status Register (RDSR) Sequence (QPI Mode)

CS#
Mode 3 0

1

2

3

4

5

6

7

N

SCLK
Mode 0

SIO[3:0]

05h H0 L0 H0 L0 H0 L0
MSB LSB Status Byte Status Byte Status Byte

H0 L0
Status Byte

P/N: PM1738

29

Rev. 1.5, September 26, 2016

MX25L25635F
9-8. Read Configuration Register (RDCR)

The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at any time (even in program/erase/write configuration register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register operation is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration Register data out on SO. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode.

Figure 19. Read Configuration Register (RDCR) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 SI High-Z command 15h Configuration register Out 7 MSB 6 5 4 3 2 1 0 7 MSB Configuration register Out 6 5 4 3 2 1 0 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SO

Figure 20. Read Configuration Register (RDCR) Sequence (QPI Mode)

CS#
Mode 3 0

1

2

3

4

5

6

7

N

SCLK
Mode 0

SIO[3:0]

15h H0 L0 H0 L0 H0 L0
MSB LSB Config. Byte Config. Byte Config. Byte

H0 L0
Config. Byte

P/N: PM1738

30

Rev. 1.5, September 26, 2016

MX25L25635F
For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:

Figure 21. Program/Erase flow with read array data
start WREN command RDSR command* No

WEL=1? Yes Program/erase command

Write program data/address (Write erase address) RDSR command No

WIP=0? Yes RDSR command

Read WEL=0, BP[3:0], QE, and SRWD data

Read array data (same address of PGM/ERS) No

Verify OK? Yes Program/erase successfully

Program/erase fail

Program/erase another block? No Program/erase completed

Yes * Issue RDSR to check BP[3:0]. * If WPSEL = 1, issue RDSPB and RDDPB to check the block status.

P/N: PM1738

31

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 22. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
start WREN command RDSR command* No

WEL=1? Yes Program/erase command

Write program data/address (Write erase address) RDSR command No

WIP=0? Yes RDSR command

Read WEL=0, BP[3:0], QE, and SRWD data RDSCUR command

P_FAIL/E_FAIL =1 ? No Program/erase successfully

Yes

Program/erase fail

Program/erase another block? No Program/erase completed
P/N: PM1738

Yes * Issue RDSR to check BP[3:0]. * If WPSEL = 1, issue RDSPB and RDDPB to check the block status.

32

Rev. 1.5, September 26, 2016

MX25L25635F
Status Register
The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs to be confirm to be 0. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in Table 2) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-protected. QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#, RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET# are disabled. In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET will be disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0".

Status Register bit7 SRWD (status register write protect)

bit6 QE (Quad Enable)

1=Quad 1=status Enable register write (note 1) (note 1) 0=not Quad disable Enable Non-volatile Non-volatile Non-volatile Non-volatile bit bit bit bit Note 1: see the Table 2 "Protected Area Size".

bit5 BP3 (level of protected block)

bit4 BP2 (level of protected block)

bit3 BP1 (level of protected block) (note 1) Non-volatile bit

bit2 BP0 (level of protected block) (note 1) Non-volatile bit

bit1

bit0

WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit

P/N: PM1738

33

Rev. 1.5, September 26, 2016

MX25L25635F
Configuration Register The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured after the CR bit is set. ODS bit The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as defined in Output Driver Strength Table) of the device. The Output Driver Strength is defaulted as 30 Ohms when delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to be executed. TB bit The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed. 4BYTE Indicator bit By writing EN4B instruction, the 4BYTE bit may be set as "1" to access the address length of 32-bit for memory area of higher density (large than 128Mb). The default state is "0" as the 24-bit address mode. The 4BYTE bit may be cleared by power-off or writing EX4B instruction to reset the state to be "0".

Table 7. Configuration Register bit7 DC1 (Dummy cycle 1) bit6 DC0 (Dummy cycle 0) bit5 4 BYTE 0=3-byte address mode 1=4-byte address mode (Default=0) volatile bit bit4 Reserved bit3 bit2 bit1 bit0 TB ODS 2 ODS 1 ODS 0 (top/bottom (output driver (output driver (output driver selected) strength) strength) strength) 0=Top area protect 1=Bottom area protect (Default=0) OTP

(note 2)

(note 2)

x

(note 1)

(note 1)

(note 1)

volatile bit

volatile bit

x

volatile bit

volatile bit

volatile bit

Note 1: see "Output Driver Strength Table" Note 2: see "Dummy Cycle and Frequency Table (MHz)"

P/N: PM1738

34

Rev. 1.5, September 26, 2016

MX25L25635F
Output Driver Strength Table ODS2 0 0 0 0 1 1 1 1 ODS1 0 0 1 1 0 0 1 1 ODS0 0 1 0 1 0 1 0 1 Description Reserved 90 Ohms 60 Ohms 45 Ohms Reserved 20 Ohms 15 Ohms 30 Ohms (Default) Note

Impedance at VCC/2

Dummy Cycle and Frequency Table (MHz) DC[1:0] 00 (default) 01 10 11 Numbers of Dummy clock cycles 8 6 8 10 Fast Read 104 104 104 133 Dual Output Fast Read 104 104 104 133 Quad Output Fast Read 104 84 104 133

DC[1:0] 00 (default) 01 10 11

Numbers of Dummy clock cycles 4 6 8 10

Dual IO Fast Read 84 104 104 133

DC[1:0] 00 (default) 01 10 11

Numbers of Dummy Quad IO Fast Read clock cycles 6 84 4 70 8 104 10 133

P/N: PM1738

35

Rev. 1.5, September 26, 2016

MX25L25635F
9-9. Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/ SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→CS# goes high. The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

Figure 23. Write Status Register (WRSR) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 command Status Register In 7 MSB 6 5 4 3 2 1 Configuration Register In 0 15 14 13 12 11 10 9 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SI

01h High-Z

SO

Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.

Figure 24. Write Status Register (WRSR) Sequence (QPI Mode)

CS#
Mode 3

0

1

2

3

4

5

Mode 3 Mode 0

SCLK
Mode 0 Command SR in H0 L0 CR in H1 L1

SIO[3:0]

01h

P/N: PM1738

36

Rev. 1.5, September 26, 2016

MX25L25635F
Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 and T/B bit, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 and T/B bit, is at software protected mode (SPM) Note: If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and T/B bit and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0 and T/B bit. If the system enter QPI or set QE=1, the feature of HPM will be disabled.

Table 8. Protection Modes Mode Software protection mode (SPM) Status register condition Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed The SRWD, BP0-BP3 of status register bits cannot be changed WP# and SRWD bit status WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 WP#=0, SRWD bit=1 Memory The protected area cannot be program or erase. The protected area cannot be program or erase.

Hardware protection mode (HPM)

Note: 1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.

P/N: PM1738

37

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 25. WRSR flow
start WREN command RDSR command No

WEL=1? Yes WRSR command

Write status register data RDSR command No

WIP=0? Yes RDSR command

Read WEL=0, BP[3:0], QE, and SRWD data No

Verify OK? Yes WRSR successfully

WRSR fail

P/N: PM1738

38

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 26. WP# Setup Timing and Hold Timing during WRSR when SRWD=1

WP# tWHSL CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14

tSHWL

15

SI High-Z

01h

SO

Note: WP# must be kept high until the embedded operation finish.

P/N: PM1738

39

Rev. 1.5, September 26, 2016

MX25L25635F
9-10. Enter 4-byte mode (EN4B) The EN4B instruction enables accessing the address length of 32-bit for the memory area of higher density (larger than 128Mb). The device default is in 24-bit address mode; after sending out the EN4B instruction, the bit5 (4BYTE bit) of security register will be automatically set to "1" to indicate the 4-byte address mode has been enabled. Once the 4-byte address mode is enabled, the address length becomes 32-bit instead of the default 24-bit. There are three methods to exit the 4-byte mode: writing exit 4-byte mode (EX4B) instruction, Reset or power-off. All instructions are accepted normally, and just the address bit is changed from 24-bit to 32-bit. The following command don't support 4bye address: 4READ fro top 128Mb (EAh), RDSFDP, RES and REMS. The sequence of issuing EN4B instruction is: CS# goes low → sending EN4B instruction to enter 4-byte mode( automatically set 4BYTE bit as "1") → CS# goes high. 9-11. Exit 4-byte mode (EX4B) The EX4B instruction is executed to exit the 4-byte address mode and return to the default 3-bytes address mode. After sending out the EX4B instruction, the bit5 (4BYTE bit) of Configuration register will be cleared to be "0" to indicate the exit of the 4-byte address mode. Once exiting the 4-byte address mode, the address length will return to 24-bit. The sequence of issuing EX4B instruction is: CS# goes low → sending EX4B instruction to exit 4-byte mode (automatically clear the 4BYTE bit to be "0") → CS# goes high.

P/N: PM1738

40

Rev. 1.5, September 26, 2016

MX25L25635F
9-12. Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte or 4-byte address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.

Figure 27. Read Data Bytes (READ) Sequence (SPI Mode only)
CS# Mode 3 SCLK Mode 0 command 24-Bit Address (Note) 23 22 21 MSB SO High-Z 7 6 3 2 1 0 Data Out 1 5 4 3 2 1 0 Data Out 2 7 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

SI

03h

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased.

P/N: PM1738

41

Rev. 1.5, September 26, 2016

MX25L25635F
9-13. Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→ 3-byte or 4-byte address on SI→ 8 dummy cycles (default)→ data out on SO→ to end FAST_ READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

P/N: PM1738

42

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 28. Read at Higher Speed (FAST_READ) Sequence (SPI Mode)
CS# Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

SCLK

Command

24-Bit Address (Note) 23 22 21 3 2 1 0

SI

0Bh High-Z

SO

CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Configurable Dummy Cycle 7 6 5 4 3 2 0 DATA OUT 1 SO 7 MSB 6 5 4 3 2 1 0 7 MSB 6 DATA OUT 2 5 4 3 2 1 0 7 MSB

SI

1

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased.

P/N: PM1738

43

Rev. 1.5, September 26, 2016

MX25L25635F
9-14. Dual Output Read Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte or 4-byte address on SIO0→ 8 dummy cycles (default) on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

Figure 29. Dual Read Mode Sequence

CS# 0 SCLK
Command

1

2

3

4

5

6

7

8

9

30 31 32

39 40 41 42 43 44 45


24 ADD Cycle A23 A22


Configurable Dummy Cycle

SI/SIO0

3B



Data Out 1

Data Out 2

A1 A0

D6 D4 D2 D0 D6 D4

SO/SIO1

High Impedance

D7 D5 D3 D1 D7 D5

Notes: 1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.

P/N: PM1738

44

Rev. 1.5, September 26, 2016

MX25L25635F
9-15. 2 x I/O Read Mode (2READ) The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 3-byte or 4-byte address interleave on SIO1 & SIO0→ 4 dummy cycles (default) on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

Figure 30. 2 x I/O Read Mode Sequence (SPI Mode only)
CS# Mode 3 SCLK Mode 0
Command 12 ADD Cycles (Note) A22 A20 A18 A4 A2 A Configurable Dummy Cycle Data Out 1 Data Out 2

0

1

2

3

4

5

6

7

8

9 10

17 18 19 20 21 22 23 24 25 26 27 28 29 30

Mode 3 Mode 0

SI/SIO0

BBh

D6 D4 D2 D0 D6 D4 D2 D0

SO/SIO1

A23 A21 A19

A5 A3 A1

D7 D5 D3 D1 D7 D5 D3 D1

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased.

P/N: PM1738

45

Rev. 1.5, September 26, 2016

MX25L25635F
9-16. Quad Read Mode (QREAD) The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte or 4-byte address on SI → 8 dummy cycle (Default) → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

Figure 31. Quad Read Mode Sequence
CS# 0 SCLK
Command

1

2

3

4

5

6

7

8

9

29 30 31 32 33

38 39 40 41 42


24 ADD Cycles


Configurable dummy cycles

Data Data Data Out 1 Out 2 Out 3
D4 D0 D4 D0 D4

SIO0

6B

A23 A22



A2 A1 A0

SIO1

High Impedance

D5 D1 D5 D1 D5

SIO2

High Impedance

D6 D2 D6 D2 D6

SIO3

High Impedance

D7 D3 D7 D3 D7

Notes: 1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.

P/N: PM1738

46

Rev. 1.5, September 26, 2016

MX25L25635F
9-17. 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B) Mode section. 4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 3-byte or 4-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. 4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence of issuing 4READ instruction QPI mode is: CS# goes low→ sending 4READ instruction→ 3-byte or 4-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

P/N: PM1738

47

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 32. 4 x I/O Read Mode Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0
Command 6 ADD Cycles Data Out 1 Data Out 2 Data Out 3

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Mode 3 Mode 0

Performance enhance indicator (Note 1)

Configurable Dummy Cycle (Note 3)

SIO0

EA/EBh

A20 A16 A12 A8 A4 A

P4 P0

D4 D0 D4 D0 D4 D0

SIO1

A21 A17 A13 A9 A5 A1 P5 P1

D5 D1 D5 D1 D5 D1

SIO2

A22 A18 A14 A10 A6 A2 P6 P2

D6 D2 D6 D2 D6 D2

SIO3

A23 A19 A15 A11 A7 A3 P7 P3

D7 D3 D7 D3 D7 D3

Notes: 1. Hi-impedance is inhibited for the two clock cycles. 2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited. 3. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. 4. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. Figure 33. 4 x I/O Read Mode Sequence (QPI Mode)
CS#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

MODE 3 MODE 0

SCLK
MODE 0

SIO[3:0]

EA/EB Data In

A5 A4 A3 A2 A1 A0
24-bit Address (Note)

X

X

X

X

X

X

H0 L0 H1 L1 H2 L2 H3 L3
MSB Data Out

Configurable Dummy Cycle

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased.

P/N: PM1738

48

Rev. 1.5, September 26, 2016

MX25L25635F
9-18. 4 Byte Address Command Set The operation of 4-byte address command set was very similar to original 3-byte address command set. The only different is all the 4-byte command set request 4-byte address (A31-A0) followed by instruction code. The command set support 4-byte address including: READ4B, Fast_Read4B, DREAD4B, 2READ4B, QREAD4B, 4READ4B, PP4B, 4PP4B, SE4B, BE32K4B, BE4B. Please note that it is not necessary to issue EN4B command before issuing any of 4-byte command set. Figure 34. Read Data Bytes using 4 Byte Address Sequence (READ4B)

CS# 0 SCLK Command 32-bit address 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47

SI

13h High Impedance

31 30 29 MSB

3

2

1

0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7

SO

MSB

Figure 35. Read Data Bytes at Higher Speed using 4 Byte Address Sequence (FASTREAD4B)
CS# 0 SCLK Command 32-bit address 1 2 3 4 5 6 7 8 9 10 36 37 38 39

SI

0Ch High Impedance

31 30 29

3

2

1

0

SO

CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Configurable Dummy cycles SI 7 6 5 4 3 2 1 0 DATA OUT 1 SO 7 6 5 4 3 2 1 0 7 6 DATA OUT 2 5 4 3 2 1 0 7
MSB

MSB

MSB

P/N: PM1738

49

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 36. 2 x I/O Fast Read using 4 Byte Address Sequence (2READ4B)
CS# Mode 3 SCLK Mode 0
Command 16 ADD Cycles Configurable Dummy Cycle Data Out 1 Data Out 2

0

1

2

3

4

5

6

7

8

9 10

21 22 23 24 25 26 27 28 29 30 31 32 33 34

Mode 3 Mode 0

SI/SIO0

BCh

A30 A28 A26

A4 A2 A

D6 D4 D2 D0 D6 D4 D2 D0

SO/SIO1

A31 A29 A27

A5 A3 A1

D7 D5 D3 D1 D7 D5 D3 D1

Figure 37. 4 I/O Fast Read using 4 Byte Address sequence (4READ4B)

CS# Mode 3 SCLK Mode 0
Command 8 ADD Cycles
Performance enhance indicator

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Mode 3 Mode 0

Data Out 1

Data Out 2

Data Out 3

Configurable Dummy Cycle D4 D0 D4 D0 D4 D0

SIO0

ECh

A28 A24 A20 A16 A12 A8 A4 A

P4 P0

SIO1

A29 A25 A21 A17 A13 A9 A5 A1 P5 P1

D5 D1 D5 D1 D5 D1

SIO2

A30 A26 A22 A18 A14 A10 A6 A2 P6 P2

D6 D2 D6 D2 D6 D2

SIO3

A31 A27 A23 A19 A15 A11 A7 A3 P7 P3

D7 D3 D7 D3 D7 D3

P/N: PM1738

50

Rev. 1.5, September 26, 2016

MX25L25635F
9-19. Burst Read The Burst Read feature allows applications to fill a cache line with a fixed length of data without using multiple read commands. Burst Read is disabled by default at power-up or reset. Burst Read is enabled by setting the Burst Length. When the Burst Length is set, reads will wrap on the selected boundary (8/16/32/64-bytes) containing the initial target address. For example if an 8-byte Wrap Depth is selected, reads will wrap on the 8-byte-page-aligned boundary containing the initial read address. To set the Burst Length, drive CS# low → send SET BURST LENGTH instruction code → send WRAP CODE → drive CS# high. Refer to the table below for valid 8-bit Wrap Codes and their corresponding Wrap Depth. Data 00h 01h 02h 03h 1xh Wrap Around Yes Yes Yes Yes No Wrap Depth 8-byte 16-byte 32-byte 64-byte X

Once Burst Read is enabled, it will remain enabled until the device is power-cycled or reset. The SPI and QPI mode 4READ and 4READ4B read commands support the wrap around feature after Burst Read is enabled. To change the wrap depth, resend the Burst Read instruction with the appropriate Wrap Code. To disable Burst Read, send the Burst Read instruction with Wrap Code 1xh. QPI “EAh” “EBh” and SPI "EAh" “EBh” support wrap around feature after wrap around is enabled. Both SPI (8 clocks) and QPI (2 clocks) command cycle can be accepted by this instruction. The SIO[3:1] are don't care during SPI mode. Figure 38. Burst Read - SPI Mode
CS#

Mode 3

0

1

2

3

4

5

6

7

8

9

10

1

12

13

14

15

SCLK
Mode 0

SIO

C0h

D7

D6

D5

D4

D3

D2

D1

D0

Figure 39. Burst Read - QPI Mode
CS#
Mode 3 0 1 2 3

SCLK
Mode 0

SIO[3:0]

C0h

H0 MSB

L0 LSB

Note: MSB=Most Significant Bit LSB=Least Significant Bit
P/N: PM1738

51

Rev. 1.5, September 26, 2016

MX25L25635F
9-20. Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. Performance enhance mode is supported in both SPI and QPI mode. In QPI mode, “EAh” “EBh” "ECh" and SPI "EAh" “EBh” "ECh" commands support enhance mode. The performance enhance mode is not supported in dual I/O mode. To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered. Issuing ”FFh” data cycle can also exit enhance mode. The system then will leave performance enhance mode and return to normal operation. After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of the first clock as address instead of command cycle. This sequence of issuing 4READ instruction is especially useful in random access : CS# goes low→send 4READ instruction→3-bytes or 4-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy cycles (Default) →data out until CS# goes high → CS# goes low (the following 4READ instruction is ignored) → 3-bytes or 4-bytes random access address. To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle(8 clocks in 3-byte address mode)/3FFh data cycle(10 clocks in 4-byte address mode), should be issued in 1I/O sequence. In QPI Mode, FFFFFFFFh data cycle(8 clocks in 3-byte address mode)/FFFFFFFFFFh data cycle (10 clocks in 4-byte address mode), in 4I/O should be issued. If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.

P/N: PM1738

52

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 40. 4 x I/O Read Performance Enhance Mode Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0
Command 6 ADD Cycles
Performance enhance indicator (Note 1)

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22

n

Data Out 1

Data Out 2

Data Out n

Configurable Dummy Cycle (Note 2)

SIO0

EBh

A20 A16 A12 A8 A4 A

P4 P0

D4 D0 D4 D0

D4 D0

SIO1

A21 A17 A13 A9 A5 A1 P5 P1

D5 D1 D5 D1

D5 D1

SIO2

A22 A18 A14 A10 A6 A2 P6 P2

D6 D2 D6 D2

D6 D2

SIO3

A23 A19 A15 A11 A7 A3 P7 P3

D7 D3 D7 D3

D7 D3

CS# n+1 SCLK
6 ADD Cycles Data Out 1 Data Out 2 Data Out n

...........

n+7 ...... n+9

........... n+13

...........

Mode 3 Mode 0

Performance enhance indicator (Note 1)

Configurable Dummy Cycle (Note 2)

SIO0

A20 A16 A12 A8 A4 A

P4 P0

D4 D0 D4 D0

D4 D0

SIO1

A21 A17 A13 A9 A5 A1 P5 P1

D5 D1 D5 D1

D5 D1

SIO2

A22 A18 A14 A10 A6 A2 P6 P2

D6 D2 D6 D2

D6 D2

SIO3

A23 A19 A15 A11 A7 A3 P7 P3

D7 D3 D7 D3

D7 D3

Notes: 1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF. 2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. 3. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased.
P/N: PM1738 Rev. 1.5, September 26, 2016

53

MX25L25635F
Figure 41. 4 x I/O Read Performance Enhance Mode Sequence (QPI Mode)
CS#
Mode 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

SCLK
Mode 0

SIO[3:0]

EBh

A5

A4

A3

A2

A1

A0 P(7:4) P(3:0)
performance enhance indicator

X

X

X

X

H0

L0

H1

L1

MSB LSB MSB LSB Data Out

Data In

Configurable Dummy Cycle (Note 1)

CS#
n+1 .............

SCLK
Mode 0

SIO[3:0]

A5

A4

A3

A2

A1

A0 P(7:4) P(3:0)

X

X

X

X

H0

L0

H1

L1

MSB LSB MSB LSB Data Out

6 Address cycles

performance enhance indicator

Configurable Dummy Cycle (Note 1)

Notes: 1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. 2. Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased.

P/N: PM1738

54

Rev. 1.5, September 26, 2016

MX25L25635F
9-21. Fast Boot The Fast Boot Feature provides the ability to automatically execute read operation after power on cycle or reset without any read instruction. A Fast Boot Register is provided on this device. It can enable the Fast Boot function and also define the number of delay cycles and start address (where boot code being transferred). Instruction WRFBR (write fast boot register) and ESFBR (erase fast boot register) can be used for the status configuration or alternation of the Fast Boot Register bit. RDFBR (read fast boot register) can be used to verify the program state of the Fast Boot Register. The default number of delay cycles is 13 cycles, and there is a 16bytes boundary address for the start of boot code access. When CS# starts to go low, data begins to output from default address after the delay cycles (default as 13 cycles). After CS# returns to go high, the device will go back to standard SPI mode and user can start to input command. In the fast boot data out process from CS# goes low to CS# goes high, a minimum of one byte must be output. Once Fast Boot feature has been enabled, the device will automatically start a read operation after power on cycle, reset command, or hardware reset operation. The fast Boot feature can support Single I/O and Quad I/O interface. If the QE bit of Status Register is “0”, the data is output by Single I/O interface. If the QE bit of Status Register is set to “1”, the data is output by Quad I/O interface.

Fast Boot Register (FBR) Bits 31 to 4 3 2 to 1 0 Description FBSA (FastBoot Start Address) x FBSD (FastBoot Start Delay Cycle) FBE (FastBoot Enable) 00: 7 delay cycles 01: 9 delay cycles 10: 11 delay cycles 11: 13 delay cycles 0=FastBoot is enabled. 1=FastBoot is not enabled. Bit Status Default State 16 bytes boundary address for the start of boot FFFFFFF code access. 1 11 1 Type NonVolatile NonVolatile NonVolatile NonVolatile

Note: If FBSD = 11, the maximum clock frequency is 133 MHz If FBSD = 10, the maximum clock frequency is 104 MHz If FBSD = 01, the maximum clock frequency is 84 MHz If FBSD = 00, the maximum clock frequency is 70 MHz

P/N: PM1738

55

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 42. Fast Boot Sequence (QE=0)
CS# Mode 3 SCLK Mode 0 SI
Delay Cycles Don’t care or High Impedance

0

-

-

-

-

-

-

n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11n+12n+13n+14n+15

Data Out 1 SO
High Impedance

Data Out 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB

7 MSB

6

5

4

3

2

Note:

If FBSD = 11, delay cycles is 13 and n is 12. If FBSD = 10, delay cycles is 11 and n is 10. If FBSD = 01, delay cycles is 9 and n is 8. If FBSD = 00, delay cycles is 7 and n is 6.

Figure 43. Fast Boot Sequence (QE=1)

CS# Mode 3 SCLK Mode 0 Delay Cycles High Impedance High Impedance High Impedance High Impedance
Data Data Out 1 Out 2 Data Out 3 Data Out 4

0

-

-

-

-

-

-

-

n

n+1 n+2 n+3 n+5 n+6 n+7 n+8 n+9

SIO0 SIO1 SIO2 SIO3

4 5 6 7 MSB

0 1 2 3

4 5 6 7

0 1 2 3

4 5 6 7

0 1 2 3

4 5 6 7

0 1 2 3

4

5 6 7

Note:

If FBSD = 11, delay cycles is 13 and n is 12. If FBSD = 10, delay cycles is 11 and n is 10. If FBSD = 01, delay cycles is 9 and n is 8. If FBSD = 00, delay cycles is 7 and n is 6.

P/N: PM1738

56

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 44. Read Fast Boot Register (RDFBR) Sequence
CS# Mode 3 SCLK Mode 0 Command 16h Data Out 1 SO High-Z 7 MSB 6 5 26 25 24 7 MSB Data Out 2 6 0 1 2 3 4 5 6 7 8 9 10 37 38 39 40 41

SI

Figure 45. Write Fast Boot Register (WRFBR) Sequence
CS# Mode 3 SCLK Mode 0 Command Fast Boot Register 0 1 2 3 4 5 6 7 8 9 10 37 38 39

SI

17h

7 MSB

6

5

26 25 24

SO

High-Z

Figure 46. Erase Fast Boot Register (ESFBR) Sequence
CS# Mode 3 SCLK Mode 0 SI Command 18h High-Z 0 1 2 3 4 5 6 7

SO

P/N: PM1738

57

Rev. 1.5, September 26, 2016

MX25L25635F
9-22. Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see "Table 4. Memory Organization") is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. Address bits [Am-A12] (Am is the most significant address) select the sector address. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte or 4-byte address on SI→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode), the Sector Erase (SE) instruction will not be executed on the block. Figure 47. Sector Erase (SE) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 Command 24-Bit Address (Note)
A23 A22 A2 A1 A0

0

1

2

3

4

5

6

7

8

9

29 30 31

SI

20h

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. Figure 48. Sector Erase (SE) Sequence (QPI Mode)
CS#
Mode 3

0

1

2

3

4

5

6

7

SCLK
Mode 0 Command 24-Bit Address (Note)

SIO[3:0]

20h A5 A4 A3 A2 A1 A0
MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased.
P/N: PM1738

58

Rev. 1.5, September 26, 2016

MX25L25635F
9-23. Block Erase (BE32K) The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 4. Memory Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A15] (Am is the most significant address) select the 32KB block address. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte or 4-byte address on SI→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode), the Block Erase (BE32K) instruction will not be executed on the block. Figure 49. Block Erase 32KB (BE32K) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 Command 24-Bit Address (Note)
A23 A22 A2 A1 A0

0

1

2

3

4

5

6

7

8

9

29 30 31

SI

52h

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. Figure 50. Block Erase 32KB (BE32K) Sequence (QPI Mode)
CS#
Mode 3

0

1

2

3

4

5

6

7

SCLK
Mode 0 Command 24-Bit Address (Note)

SIO[3:0]

52h

A5 A4 A3 A2 A1 A0
MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased.

P/N: PM1738

59

Rev. 1.5, September 26, 2016

MX25L25635F
9-24. Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte or 4-byte address on SI→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode), the Block Erase (BE) instruction will not be executed on the block. Figure 51. Block Erase (BE) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 Command 24-Bit Address (Note)
A23 A22 A2 A1 A0

0

1

2

3

4

5

6

7

8

9

29 30 31

SI

D8h

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased. Figure 52. Block Erase (BE) Sequence (QPI Mode)
CS#
Mode 3

0

1

2

3

4

5

6

7

SCLK
Mode 0 Command 24-Bit Address (Note)

SIO[3:0]

D8h

A5 A4 A3 A2 A1 A0
MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased.
P/N: PM1738

60

Rev. 1.5, September 26, 2016

MX25L25635F
9-25. Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. When the chip is under "Block protect (BP) Mode" (WPSEL=0). The Chip Erase (CE) instruction will not be executed, if one (or more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0". When the chip is under "Advances Sector Protect Mode" (WPSEL=1). The Chip Erase (CE) instruction will be executed on unprotected block. The protected Block will be skipped. If one (or more) 4K byte sector was protected in top or bottom 64K byte block, the protected block will also skip the chip erase command.

Figure 53. Chip Erase (CE) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 SI Command 60h or C7h 0 1 2 3 4 5 6 7

Figure 54. Chip Erase (CE) Sequence (QPI Mode)
CS#
Mode 3
0 1

SCLK
Mode 0
Command 60h or C7h

SIO[3:0]

P/N: PM1738

61

Rev. 1.5, September 26, 2016

MX25L25635F
9-26. Page Program (PP) The Page Program (PP) instruction is for programming memory bits to "0". One to 256 bytes can be sent to the device to be programmed. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If more than 256 data bytes are sent to the device, only the last 256 data bytes will be accepted and the previous data bytes will be disregarded. The Page Program instruction requires that all the data bytes fall within the same 256-byte page. The low order address byte A[7:0] specifies the starting address within the selected page. Bytes that will cross a page boundary will wrap to the beginning of the selected page. The device can accept (256 minus A[7:0]) data bytes without wrapping. If 256 data bytes are going to be programmed, A[7:0] should be set to 0. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte or 4-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode), the Page Program (PP) instruction will not be executed. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode.

P/N: PM1738

62

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 55. Page Program (PP) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 Command 24-Bit Address (Note) 23 22 21 MSB 3 2 1 0 7 6 Data Byte 1 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

SI

02h

5

4

3

2

1

0

MSB

CS# 2072 2073 2074 2075 2076 2077 2 2078 1 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Data Byte 2 Data Byte 3 Data Byte 256 2079 0

SI

7

6

5

4

3

2

1

0

7 MSB

6

5

4

3

2

1

0

7

6

5

4

3

MSB

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased.

Figure 56. Page Program (PP) Sequence (QPI Mode)
CS#
Mode 3

0

1

2

SCLK
Mode 0 Command 24-Bit Address (Note)

SIO[3:0]

02h Data In

A5

A4

A3

A2

A1

A0

H0

L0

H1

L1

H2

L2

H3

L3

H255 L255

Data Byte Data Byte Data Byte Data Byte 1 2 3 4

Data Byte 256

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased.

P/N: PM1738

63

Rev. 1.5, September 26, 2016

MX25L25635F
9-27. 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of application. The other function descriptions are as same as standard page program. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte or 4-byte address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high. If the page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode), the Quad Page Program (4PP) instruction will not be executed.

Figure 57. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)

CS# Mode 3 SCLK Mode 0 Command 6 Address cycle Data Data Data Data Byte 1 Byte 2 Byte 3 Byte 4
A0

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21

SIO0 SIO1 SIO2 SIO3

38h

A20 A16 A12 A8 A4

4 5 6 7

0 1 2 3

4 5 6 7

0 1 2 3

4 5 6 7

0 1 2 3

4 5 6 7

0 1 2 3

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

A23 A19 A15 A11 A7 A3

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the address cycles will be increased.

P/N: PM1738

64

Rev. 1.5, September 26, 2016

MX25L25635F
9-28. Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode.

Figure 58. Deep Power-down (DP) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 SI Command B9h Stand-by Mode Deep Power-down Mode 0 1 2 3 4 5 6 7 tDP

Figure 59. Deep Power-down (DP) Sequence (QPI Mode)
CS#
Mode 3

0

1

tDP

SCLK
Mode 0 Command

SIO[3:0]

B9h

Stand-by Mode

Deep Power-down Mode

P/N: PM1738

65

Rev. 1.5, September 26, 2016

MX25L25635F
9-29. Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit secured OTP mode. While device is in 4K-bit secured OTPmode, main array access is not available. The additional 4K-bit secured OTP is independent from main array and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Please note that after issuing ENSO command user can only access secure OTP region with standard read or program procedure. Furthermore, once security OTP is lock down, only read related commands are valid. 9-30. Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-31. Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register data out on SO→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-32. Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM1738

66

Rev. 1.5, September 26, 2016

MX25L25635F
Security Register The definition of the Security Register bits is as below: Write Protection Selection bit. Please reference to "Write Protection Selection bit" Erase Fail bit. The Erase Fail bit is a status flag, which shows the status of last Erase operation. It will be set to "1", if the erase operation fails. It will be set to "0", if the last operation is success. Please note that it will not interrupt or stop any operation in the flash memory. Program Fail bit. The Program Fail bit is a status flag, which shows the status of last Program operation. It will be set to "1", if the program operation fails or the program region is protected. It will be set to "0", if the last operation is success. Please note that it will not interrupt or stop any operation in the flash memory. Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is cleared to "0" after erase operation resumes. Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes. Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be updated any more. While it is in 4K-bit secured OTP mode, main array access is not allowed. Table 9. Security Register Definition bit7 WPSEL bit6 E_FAIL 0=normal Erase succeed 1=indicate Erase failed (default=0) Volatile bit bit5 P_FAIL 0=normal Program succeed 1=indicate Program failed (default=0) Volatile bit bit4 Reserved bit3 bit2 bit1 bit0 ESB PSB (Erase (Program Suspend bit) Suspend bit) 0=Erase is not suspended 1= Erase suspended (default=0) Volatile bit LDSO Secured OTP (indicate if indicator bit lock-down)

0=normal WP mode 1=individual mode (default=0) Non-volatile bit (OTP)

-

Volatile bit

0 = not lock0=Program 0 = nondown is not factory 1 = lock-down suspended lock (cannot 1= Program 1 = factory program/ suspended lock erase (default=0) OTP) Non-volatile Non-volatile Volatile bit bit bit (OTP) (OTP)

P/N: PM1738

67

Rev. 1.5, September 26, 2016

MX25L25635F
9-33. Write Protection Selection (WPSEL) There are two write protection methods provided on this device, (1) Block Protection (BP) mode or (2) Advanced Sector Protection mode. The protection modes are mutually exclusive. The WPSEL bit selects which protection mode is enabled. If WPSEL=0 (factory default), BP mode is enabled and Advanced Sector Protection mode is disabled. If WPSEL=1, Advanced Sector Protection mode is enabled and BP mode is disabled. The WPSEL command is used to set WPSEL=1. A WREN command must be executed to set the WEL bit before sending the WPSEL command. Please note that the WPSEL bit is an OTP bit. Once WPSEL is set to “1”, it cannot be programmed back to “0”. When WPSEL = 0: Block Protection (BP) mode, The memory array is write protected by the BP3~BP0 bits. When WPSEL =1: Advanced Sector Protection mode, Blocks are individually protected by their own SPB or DPB. On power-up, all blocks are write protected by the Dynamic Protection Bits (DPB) by default. The Advanced Sector Protection instructions WRLR, RDLR, WRPASS, RDPASS, PASSULK, WRSPB, ESSPB, SPBLK, RDSPBLK, WRDPB, RDDPB, GBLK, and GBULK are activated. The BP3~BP0 bits of the Status Register are disabled and have no effect. Hardware protection is performed by driving WP#=0. Once WP#=0 all blocks and sectors are write protected regardless of the state of each SPB or DPB. The sequence of issuing WPSEL instruction is: CS# goes low → send WPSEL instruction to enable the Advanced Sector Protect mode → CS# goes high.

Write Protection Selection
Start (Default in BP Mode)

WPSEL=1

Set WPSEL Bit

WPSEL=0

Advance Sector Protection

Block Protection (BP)

Set Lock Register Bit 2 =0 Password Protection

Bit 1 =0

Solid Protection

Dynamic Protection

P/N: PM1738

68

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 60. WPSEL Flow
start

WREN command

RDSCUR command

WPSEL=1? No WPSEL disable, block protected by BP[3:0]

Yes

WPSEL command

RDSR command

WIP=0? Yes RDSCUR command

No

WPSEL=1? Yes WPSEL set successfully

No

WPSEL set fail

Block protected by Advance Sector Protection

WPSEL enable.

P/N: PM1738

69

Rev. 1.5, September 26, 2016

MX25L25635F
9-34. Advanced Sector Protection Advanced Sector Protection can protect individual 4KB sectors in the bottom and top 64KB of memory and protect individual 64KB blocks in the rest of memory. There is one non-volatile Solid Protection Bit (SPB) and one volatile Dynamic Protection Bit (DPB) assigned to each 4KB sector at the bottom and top 64KB of memory and to each 64KB block in the rest of memory. A sector or block is write-protected from programming or erasing when its associated SPB or DPB is set to “1”. The Unprotect Solid Protect Bit (USPB) can temporarily override and disable the write-protection provided by the SPB bits. There are two mutually exclusive implementations of Advanced Sector Protection: Solid Protection mode (factory default) and Password Protection mode. Solid Protection mode permits the SPB bits to be modified after power-on or a reset. The Password Protection mode requires a valid password before allowing the SPB bits to be modified. The figure below is an overview of Advanced Sector Protection. Figure 61. Advanced Sector Protection Overview
Start

Bit 1=0

Set Lock Register ?

Bit 2=0

Solid Protection Mode

Password Protection Mode

Set 64 bit Password

Set SPB Lock Bit ?

SPBLK = 0

All SPB can not be changeable

SPB Lock bit locked

SPBLK = 1 SPB Lock bit Unlocked SPB is changeable

Dynamic Protect Bit Register (DPB) DPB=1 sector protect DPB=0 sector unprotect Sector Array

SPB Access Register (SPB) SPB=1 Write Protect SPB=0 Write Unprotect

Temporary Unprotect SPB bit (USPB) USPB=0 SPB bit is disabled USPB=1 SPB bit is effective

DPB 0 DPB 1 DPB 2 : : DPB N-1 DPB N

SA 0 SA 1 SA 2 : : SA N-1 SA N

SPB 0 SPB 1 SPB 2 : : SPB N-1 SPB N USPB

P/N: PM1738

70

Rev. 1.5, September 26, 2016

MX25L25635F
9-34-1. Lock Register The Lock Register is a 16-bit one-time programmable register. Lock Register bits [2:1] select between Solid Protection mode and Password Protection mode. When both bits are “1” (factory default), Solid Protection mode is enabled by default. The Lock Register is programmed using the WRLR (Write Lock Register) command. Programming Lock Register bit 1 to “0” permanently selects Solid Protection mode and permanently disables Password Protection mode. Conversely, programming bit 2 to “0” permanently selects Password Protection mode and permanently disables Solid Protection mode. Bits 1 and 2 cannot be programmed to “0” at the same time otherwise the device will abort the operation. A WREN command must be executed to set the WEL bit before sending the WRLR command. A password must be set prior to selecting Password Protection mode. The password can be set by issuing the WRPASS command. Lock Register Bit 15-3 Bit 2 Bit 1 Bit0 Reserved Password Protection Mode Lock Bit Solid Protection Mode Lock Bit Reserved 0=Password Protection Mode Enable 0=Solid Protection Mode Enable x 1= Password Protection Mode not x 1= Solid Protection Mode not enable (Default =1) enable (Default =1) OTP OTP OTP OTP Note: Once bit 2 or bit 1 has been programmed to "0", the other bit can't be changed any more. Attempts to clear more than one bit in the Lock Register will set the Security Register P_FAIL flag to "1". Figure 62. Read Lock Register (RDLR) Sequence
CS# Mode 3 SCLK Mode 0 SI High-Z command 2Dh Register Out 7 MSB 6 5 4 3 2 1 Register Out 0 15 14 13 12 11 10 9 MSB 8 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SO

Figure 63. Write Lock Register (WRLR) Sequence (SPI Mode)
CS# Mode 3 SCLK Mode 0 Command Lock Register In 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SI

2Ch High-Z

7 MSB

6

5

4

3

2

1

0 15 14 13 12 11 10 9

8

SO

P/N: PM1738

71

Rev. 1.5, September 26, 2016

MX25L25635F
9-34-2. SPB Lock Bit (SPBLK) The SPB Lock Bit (SPBLK) is a volatile bit located in bit 0 of the SPB Lock Register. The SPBLK bit controls whether the SPB bits can be modified or not. If SPBLK=1, the SPB bits are unprotected and can be modified. If SPBLK=0, the SPB bits are protected (“locked”) and cannot be modified. The power-on and reset status of the SPBLK bit is determined by Lock Register bits [2:1]. Refer to SPB Lock Register for SPBLK bit default power-on status. The RDSPBLK command can be used to read the SPB Lock Register to determine the state of the SPBLK bit. In Solid Protection mode, the SPBLK bit defaults to “1” after power-on or reset. When SPBLK=1, the SPB bits are unprotected (“unlocked”) and can be modified. The SPB Lock Bit Set command can be used to write the SPBLK bit to “0” and protect the SPB bits. A WREN command must be executed to set the WEL bit before sending the SPB Lock Bit Set command. Once the SPBLK has been written to “0”, there is no command (except a software reset) to set the bit back to “1”. A power-on cycle or reset is required to set the SPB lock bit back to “1”. In Password Protection mode, the SPBLK bit defaults to “0” after power-on or reset. A valid password must be provided to set the SPBLK bit to “1” to allow the SPBs to be modified. After the SPBs have been set to the desired status, use the SPB Lock Bit Set command to clear the SPBLK bit back to “0” in order to prevent further modification. SPB Lock Register Bit Description 7-1 Reserved 0 SPBLK (SPB Lock Bit) Bit Status X 0 = SPBs protected 1= SPBs unprotected Default 0000000 Solid Protection Mode: 1 Password Protection Mode: 0 Type Volatile Volatile

Figure 64. SPB Lock Bit Set (SPBLK) Sequence
CS# Mode 3 SCLK Mode 0 SI Command A6h High-Z 0 1 2 3 4 5 6 7

SO

Figure 65. Read SPB Lock Register (RDSPBLK) Sequence
CS# Mode 3 SCLK Mode 0 SI High-Z command A7h Register Out 7 MSB 6 5 4 3 2 1 0 7 MSB 6 Register Out 5 4 3 2 1 0 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SO

P/N: PM1738

72

Rev. 1.5, September 26, 2016

MX25L25635F
9-34-3. Solid Protection Bits The Solid Protection Bits (SPBs) are nonvolatile bits for enabling or disabling write-protection to sectors and blocks. The SPB bits have the same endurance as the Flash memory. An SPB is assigned to each 4KB sector in the bottom and top 64KB of memory and to each 64KB block in the remaining memory. The factory default state of the SPB bits is “0”, which has the sector/block write-protection disabled. When an SPB is set to “1”, the associated sector or block is write-protected. Program and erase operations on the sector or block will be inhibited. SPBs can be individually set to “1” by the WRSPB command. However, the SPBs cannot be individually cleared to “0”. Issuing the ESSPB command clears all SPBs to “0”. A WREN command must be executed to set the WEL bit before sending the WRSPB or ESSPB command. The SPBLK bit must be “1” before any SPB can be modified. In Solid Protection mode the SPBLK bit defaults to “1” after power-on or reset. Under Password Protection mode, the SPBLK bit defaults to “0” after power-on or reset, and a PASSULK command with a correct password is required to set the SPBLK bit to “1”. The SPB Lock Bit Set command clears the SPBLK bit to “0”, locking the SPB bits from further modification. The RDSPB command reads the status of the SPB of a sector or block. The RDSPB command returns 00h if the SPB is “0”, indicating write-protection is disabled. The RDSPB command returns FFh if the SPB is “1”, indicating write-protection is enabled. In Solid Protection mode, the Unprotect Solid Protect Bit (USPB) can temporarily mask the SPB bits and disable the write-protection provided by the SPB bits. Note: If SPBLK=0, commands to set or clear the SPB bits will be ignored.

SPB Register Bit Description 7 to 0 SPB (Solid Protection Bit) Bit Status 00h = Unprotect Sector / Block FFh = Protect Sector / Block Default 00h Type Non-volatile

P/N: PM1738

73

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 66. Read SPB Status (RDSPB) Sequence
CS# Mode 3 SCLK Mode 0 Command E2h
A31 A30

0

1

2

3

4

5

6

7

8

9

37 38 39 40 41 42 43 44 45 46 47

32-Bit Address
A2 A1 A0

SI

MSB SO High-Z 7 MSB 6

Data Out 5 4 3 2 1 0

Figure 67. SPB Erase (ESSPB) Sequence
CS# Mode 3 SCLK Mode 0 SI Command E4h High-Z 0 1 2 3 4 5 6 7

SO

Figure 68. SPB Program (WRSPB) Sequence
CS# Mode 3 SCLK Mode 0 Command 32-Bit Address 0 1 2 3 4 5 6 7 8 9 37 38 39

SI

E3h

A31 A30

A2 A1 A0

MSB

P/N: PM1738

74

Rev. 1.5, September 26, 2016

MX25L25635F
9-34-4. Dynamic Protection Bits The Dynamic Protection Bits (DPBs) are volatile bits for quickly and easily enabling or disabling write-protection to sectors and blocks. A DPB is assigned to each 4KB sector in the bottom and top 64KB of memory and to each 64KB block in the rest of the memory. The DBPs can enable write-protection on a sector or block regardless of the state of the corresponding SPB. However, the DPB bits can only unprotect sectors or blocks whose SPB bits are “0” (unprotected). When a DPB is “1”, the associated sector or block will be write-protected, preventing any program or erase operation on the sector or block. All DPBs default to “1” after power-on or reset. When a DPB is cleared to “0”, the associated sector or block will be unprotected if the corresponding SPB is also “0”. DPB bits can be individually set to “1” or “0” by the WRDPB command. The DBP bits can also be globally cleared to “0” with the GBULK command or globally set to “1” with the GBLK command. A WREN command must be executed to set the WEL bit before sending the WRDPB, GBULK, or GBLK command. The RDDPB command reads the status of the DPB of a sector or block. The RDDPB command returns 00h if the DPB is “0”, indicating write-protection is disabled. The RDDPB command returns FFh if the DPB is “1”, indicating write-protection is enabled. DPB Register Bit Description Bit Status 00h = Unprotect Sector / Block FFh = Protect Sector / Block Default FFh Type Volatile

7 to 0 DPB (Dynamic Protection Bit)

Figure 69. Read DPB Register (RDDPB) Sequence
CS# Mode 3 SCLK Mode 0 Command E0h
A31 A30

0

1

2

3

4

5

6

7

8

9

37 38 39 40 41 42 43 44 45 46 47

32-Bit Address
A2 A1 A0

SI

MSB SO High-Z 7 MSB 6

Data Out 5 4 3 2 1 0

Figure 70. Write DPB Register (WRDPB) Sequence
CS# Mode 3 SCLK Mode 0 Command E1h
A31 A30

0

1

2

3

4

5

6

7

8

9

37 38 39 40 41 42 43 44 45 46 47

32-Bit Address
A2 A1 A0

Data Byte 1 7 MSB 6 5 4 3 2 1 0

SI

MSB

P/N: PM1738

75

Rev. 1.5, September 26, 2016

MX25L25635F
9-34-5. Unprotect Solid Protect Bit (USPB) The Unprotect Solid Protect Bit is a volatile bit that defaults to “1” after power-on or reset. When USPB=1, the SPBs have their normal function. When USPB=0 all SPBs are masked and their write-protected sectors and blocks are temporarily unprotected (as long as their corresponding DPBs are “0“). The USPB provides a means to temporarily override the SPBs without having to issue the ESSPB and WRSPB commands to clear and set the SPBs. The USPB can be set or cleared as often as needed. Please refer to 9-35-7. Sector Protection States Summary Table" for the sector state with the protection status of DPB/SPB/USPB bits. 9-34-6. Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only effective if WPSEL=1. The GBLK and GBULK instructions provide a quick method to set or clear all DPB bits at once. The WREN (Write Enable) instruction is required before issuing the GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →CS# goes high. The GBLK and GBULK commands are accepted in both SPI and QPI mode. The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.

9-34-7. Sector Protection States Summary Table Protection Status DPB 0 0 0 0 1 1 1 1 SPB 0 0 1 1 0 0 1 1 USPB 0 1 0 1 0 1 0 1 Sector/Block Protection State Unprotected Unprotected Unprotected Protected Protected Protected Protected Protected

P/N: PM1738

76

Rev. 1.5, September 26, 2016

MX25L25635F
9-34-8. Password Protection Mode Password Protection mode potentially provides a higher level of security than Solid Protection mode. In Password Protection mode, the SPBLK bit defaults to “0” after a power-on cycle or reset. When SPBLK=0, the SPBs are locked and cannot be modified. A 64-bit password must be provided to unlock the SPBs. The PASSULK command with the correct password will set the SPBLK bit to “1” and unlock the SPB bits. After the correct password is given, a wait of 2us is necessary for the SPB bits to unlock. The Status Register WIP bit will clear to “0” upon completion of the PASSULK command. Once unlocked, the SPB bits can be modified. A WREN command must be executed to set the WEL bit before sending the PASSULK command. Several steps are required to place the device in Password Protection mode. Prior to entering the Password Protection mode, it is necessary to set the 64-bit password and verify it. The WRPASS command writes the password and the RDPASS command reads back the password. Password verification is permitted until the Password Protection Mode Lock Bit has been written to “0”. Password Protection mode is activated by programming the Password Protection Mode Lock Bit to “0”. This operation is not reversible. Once the bit is programmed, it cannot be erased. The device remains permanently in Password Protection mode and the 64-bit password can neither be retrieved nor reprogrammed.. The password is all “1’s” when shipped from the factory. The WRPASS command can only program password bits to “0”. The WRPASS command cannot program “0’s” back to “1’s”. All 64-bit password combinations are valid password options. A WREN command must be executed to set the WEL bit before sending the WRPASS command. ● The unlock operation will fail if the password provided by the PASSULK command does not match the stored password. This will set the P_ERR bit to “1” and insert a 100us ± 20us delay before clearing the WIP bit to “0”. ● The PASSULK command is prohibited from being executed faster than once every 100us ± 20us. This restriction makes it impractical to attempt all combinations of a 64-bit password (such an effort would take ~58 million years). Monitor the WIP bit to determine whether the device has completed the PASSULK command. ● When a valid password is provided, the PASSULK command does not insert the 100us delay before returning the WIP bit to zero. The SPBLK bit will set to “1” and the P_ERR bit will be “0”. ● It is not possible to set the SPBLK bit to “1” if the password had not been set prior to the Password Protection mode being selected.

Password Register (PASS) Bits Field Function Type Name Default State Description

63 to 0 PWD

Non-volatile OTP storage of 64 bit password. The Hidden password is no longer readable after the Password OTP FFFFFFFFFFFFFFFFh Password Protection mode is selected by programming Lock Register bit 2 to zero.

P/N: PM1738

77

Rev. 1.5, September 26, 2016

MX25L25635F
9-35. Program/Erase Suspend/Resume The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other operations. After issue suspend command, the system can determine if the device has entered the Erase-Suspended mode through Bit2 (PSB) and Bit3 (ESB) of security register. (please refer to "Table 9. Security Register Definition") The latency time of erase operation: Suspend to suspend ready timing: 20us. Resume to another suspend timing: 1ms. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-36. Erase Suspend Erase suspend allow the interruption of all erase operations. After the device has entered Erase-Suspended mode, the system can read any sector(s) or Block(s) except those being erased by the suspended erase operation. Reading the sector or Block being erase suspended is invalid. After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted. (including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h, 00h, 35h, F5h, 15h, 2Dh, 27h, A7h, E2h, E0h, 16h) If the system issues an Erase Suspend command after the sector erase operation has already begun, the device will not enter Erase-Suspended mode until 20us time has elapsed. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is cleared to "0" after erase operation resumes. 9-37. Program Suspend Program suspend allows the interruption of all program operations. After the device has entered ProgramSuspended mode, the system can read any sector(s) or Block(s) except those be? ing programmed by the suspended program operation. Reading the sector or Block being program suspended is invalid. After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h, 00h, 35h, F5h, 15h, 2Dh, 27h, A7h, E2h, E0h, 16h) Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes.

P/N: PM1738

78

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 71. Suspend to Read Latency
Program latency : 20us Erase latency:20us

CS#

Suspend Command [B0]

Read Command

Figure 72. Resume to Read Latency
TSE/TBE/TPP Read Command

CS#

Resume Command [30]

Figure 73. Resume to Suspend Latency

CS#

Resume Command [30]

1ms

Suspend Command [B0]

P/N: PM1738

79

Rev. 1.5, September 26, 2016

MX25L25635F
9-38. Write-Resume The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in Status register will be changed back to “0”. The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30H) → drive CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed or not. The user may also wait the time lag of TSE, TBE, TPP for Sector-erase, Block-erase or Page-programming. WREN (command "06") is not required to issue before resume. Resume to another suspend operation requires latency time of 1ms. Please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resumed. To restart the write command, disable the "performance enhance mode" is required. After the "performance enhance mode" is disabled, the write-resume command is effective. 9-39. No Operation (NOP) The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any other command. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care during SPI mode. 9-40. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST) command. It returns the device to standby mode. All the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will be invalid. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. If the Reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. The reset time is different depending on the last operation. For details, please refer to "Table 14. Reset Timing(Other Operation)" for tREADY2.

P/N: PM1738

80

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 74. Software Reset Recovery

Stand-by Mode

CS#

66

99
tReady2

Mode

Note: Refer to "Table 14. Reset Timing-(Other Operation)" for tREADY2 data. Figure 75. Reset Sequence (SPI mode)
tSHSL

CS#
Mode 3 Mode 3 Mode 0
Command Command

SCLK

Mode 0

SIO0

66h

99h

Figure 76. Reset Sequence (QPI mode)
tSHSL

CS#
MODE 3 MODE 3 MODE 0 MODE 3 MODE 0

SCLK
MODE 0
Command Command

SIO[3:0]

66h

99h

P/N: PM1738

81

Rev. 1.5, September 26, 2016

MX25L25635F
9-41. Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a JEDEC standard, JESD216.

Figure 77. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence

CS# 0 SCLK Command 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 28 29 30 31

SI

5Ah High-Z

23 22 21

3

2

1

0

SO

CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle

SI

7

6

5

4

3

2

1

0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB

SO

7 MSB

6

5

4

3

2

P/N: PM1738

82

Rev. 1.5, September 26, 2016

MX25L25635F
Table 10. Signature and Parameter Identification Data Values Description Comment Add (h) DW Add (Byte) (Bit) 00h 07:00 01h 02h 03h SFDP Minor Revision Number SFDP Major Revision Number Number of Parameter Headers Unused ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) Unused ID number (Macronix manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) Unused it indicates Macronix manufacturer ID Start from 00h Start from 01h How many DWORDs in the Parameter table First address of Macronix Flash Parameter table 00h: it indicates a JEDEC specified header. Start from 00h Start from 01h How many DWORDs in the Parameter table First address of JEDEC Flash Parameter table Start from 00h Start from 01h This number is 0-based. Therefore, 0 indicates 1 parameter header. 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 15:08 23:16 31:24 07:00 15:08 23:16 31:24 07:00 15:08 23:16 31:24 07:00 15:08 23:16 31:24 07:00 15:08 23:16 31:24 07:00 15:08 23:16 31:24 Data (h/b) note1 53h 46h 44h 50h 00h 01h 01h FFh 00h 00h 01h 09h 30h 00h 00h FFh C2h 00h 01h 04h 60h 00h 00h FFh Data (h) 53h 46h 44h 50h 00h 01h 01h FFh 00h 00h 01h 09h 30h 00h 00h FFh C2h 00h 01h 04h 60h 00h 00h FFh

SFDP Signature

Fixed: 50444653h

P/N: PM1738

83

Rev. 1.5, September 26, 2016

MX25L25635F
Table 11. Parameter Table (0): JEDEC Flash Parameter Tables Description Block/Sector Erase sizes Write Granularity Comment 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not support 4KB erase 0: 1Byte, 1: 64Byte or larger Add (h) DW Add (Byte) (Bit) 01:00 02 03 30h 04 0b Data (h/b) note1 01b 1b 0b E5h Data (h)

Write Enable Instruction Required 0: not required 1: required 00h to be written to the for Writing to Volatile Status status register Registers 0: use 50h opcode, 1: use 06h opcode Write Enable Opcode Select for Note: If target flash status register is Writing to Volatile Status Registers nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be Unused changed 4KB Erase Opcode (1-1-2) Fast Read (Note2) Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) Clocking (1-2-2) Fast Read (1-4-4) Fast Read (1-1-4) Fast Read Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states (Note3) Clocks) not support (1-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits (Note4) (1-4-4) Fast Read Opcode (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-4) Fast Read Number of 000b: Mode Bits not support Mode Bits (1-1-4) Fast Read Opcode 0=not support 1=support 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved 0=not support 1=support 0=not support 1=support 0=not support 1=support 0=not support 1=support

07:05 31h 15:08 16 18:17 19 32h 20 21 22 23 33h 37h:34h 38h 39h 3Ah 3Bh 31:24 31:00 04:00 07:05 15:08 20:16 23:21 31:24

111b 20h 1b 01b 0b 1b 1b 1b 1b FFh FFh F3h 20h

0FFF FFFFh 0 0100b 010b EBh 0 1000b 000b 6Bh 44h EBh 08h 6Bh

P/N: PM1738

84

Rev. 1.5, September 26, 2016

MX25L25635F
Description Comment Add (h) DW Add (Byte) (Bit) 3Ch 3Dh 3Eh 3Fh 0=not support 1=support 40h 04:00 07:05 15:08 20:16 23:21 31:24 00 03:01 04 07:05 43h:41h 45h:44h 46h 47h 49h:48h 4Ah 4Bh Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist
(Note5)

(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not supported (1-1-2) Fast Read Number of 000b: Mode Bits not supported Mode Bits (1-1-2) Fast Read Opcode (1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not supported (1-2-2) Fast Read Number of 000b: Mode Bits not supported Mode Bits (1-2-2) Fast Read Opcode (2-2-2) Fast Read Unused (4-4-4) Fast Read Unused Unused Unused (2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not supported (2-2-2) Fast Read Number of 000b: Mode Bits not supported Mode Bits (2-2-2) Fast Read Opcode Unused (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not supported (4-4-4) Fast Read Number of 000b: Mode Bits not supported Mode Bits (4-4-4) Fast Read Opcode Sector Type 1 Size Sector Type 1 erase Opcode Sector Type 2 Size Sector Type 2 erase Opcode Sector Type 3 Size Sector Type 3 erase Opcode Sector Type 4 Size Sector Type 4 erase Opcode 0=not support 1=support

Data (h/b) note1 0 1000b 000b 3Bh 0 0100b 000b BBh 0b 111b 1b 111b FFh FFh 0 0000b 000b FFh FFh 0 0100b 010b EBh 0Ch 20h 0Fh 52h 10h D8h 00h FFh

Data (h) 08h 3Bh 04h BBh

FEh

31:08 15:00 20:16 23:21 31:24 15:00 20:16 23:21 31:24 07:00 15:08 23:16 31:24 07:00 15:08 23:16 31:24

FFh FFh 00h FFh FFh 44h EBh 0Ch 20h 0Fh 52h 10h D8h 00h FFh

4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h

P/N: PM1738

85

Rev. 1.5, September 26, 2016

MX25L25635F
Table 12. Parameter Table (1): Macronix Flash Parameter Tables Description Vcc Supply Maximum Voltage Comment 2000h=2.000V 2700h=2.700V 3600h=3.600V 1650h=1.650V 2250h=2.250V 2350h=2.350V 2700h=2.700V 0=not support 1=support 0=not support 1=support 0=not support 1=support 0=not support 1=support Reset Enable (66h) should be issued 65h:64h before Reset Opcode. 0=not support 1=support 0=not support 1=support Add (h) DW Add (Byte) (Bit) 61h:60h 07:00 15:08 23:16 31:24 00 01 02 03 11:04 12 13 14 0=not support 1=support 66h 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B 0=not support 1=support 0=Volatile 1=Nonvolatile 67h 15 23:16 31:24 00 01 09:02 0=protect 1=unprotect 0=not support 1=support 0=not support 1=support 0=not support 1=support 6Bh:68h 10 11 12 13 15:14 31:16 6Fh:6Ch [31:00] Data (h/b) note1 00h 36h 00h 27h 1b 0b 1b 1b 1001 1001b F99Dh (99h) 1b 1b 1b 1b C0h 64h 1b 0b 1110 0001b (E1h) 0b 1b 0b 0b 11b FFh FFh FFh FFh CB85h C0h 64h Data (h) 00h 36h 00h 27h

Vcc Supply Minimum Voltage H/W Reset# pin H/W Hold# pin Deep Power Down Mode S/W Reset S/W Reset Opcode Program Suspend/Resume Erase Suspend/Resume Unused Wrap-Around Read mode Wrap-Around Read mode Opcode Wrap-Around Read data length Individual block lock Individual block lock bit (Volatile/Nonvolatile) Individual block lock Opcode Individual block lock Volatile protect bit default protect status Secured OTP Read Lock Permanent Lock Unused Unused Unused

63h:62h

P/N: PM1738

86

Rev. 1.5, September 26, 2016

MX25L25635F
Note 1: h/b is hexadecimal or binary. Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix.

P/N: PM1738

87

Rev. 1.5, September 26, 2016

MX25L25635F
10. RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at the following states: - Standby mode - All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on. - 3-byte address mode If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to minimum. Figure 78. RESET Timing

CS#

tRHSL

SCLK
tRH tRS

RESET# tRLRH tREADY1 / tREADY2

Table 13. Reset Timing-(Power On) Symbol Parameter tRHSL Reset# high before CS# low tRS Reset# setup time tRH Reset# hold time tRLRH Reset# low pulse width tREADY1 Reset Recovery time Table 14. Reset Timing-(Other Operation) Parameter Reset# high before CS# low Reset# setup time Reset# hold time Reset# low pulse width Reset Recovery time (During instruction decoding) Reset Recovery time (for read operation) Reset Recovery time (for program operation) tREADY2 Reset Recovery time(for SE4KB operation) Reset Recovery time (for BE64K/BE32KB operation) Reset Recovery time (for Chip Erase operation) Reset Recovery time (for WRSR operation)
P/N: PM1738

Min. 10 15 15 10 35

Typ.

Max.

Unit us ns ns us us

Symbol tRHSL tRS tRH tRLRH

Min. 10 15 15 10 40 35 310 12 25 100 40

Typ.

Max.

Unit us ns ns us us us us ms ms ms ms

88

Rev. 1.5, September 26, 2016

MX25L25635F
11. POWER-ON STATE
The device is at below states when power-up: - Standby mode (please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) - At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.

P/N: PM1738

89

Rev. 1.5, September 26, 2016

MX25L25635F
12. ELECTRICAL SPECIFICATIONS
Table 15. ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential Industrial grade VALUE -40°C to 85°C -65°C to 150°C -0.5V to VCC+0.5V -0.5V to VCC+0.5V -0.5V to 4.0V

NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see "Figure 79. Maximum Negative Overshoot Waveform" and "Figure 80. Maximum Positive Overshoot Waveform".

Figure 79. Maximum Negative Overshoot Waveform
20ns 20ns

Figure 80. Maximum Positive Overshoot Waveform
20ns

Vss

Vcc + 2.0V

Vss-2.0V
20ns

Vcc
20ns 20ns

Table 16. CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol Parameter CIN COUT Input Capacitance Output Capacitance Min. Typ. Max. 6 8 Unit pF pF Conditions VIN = 0V VOUT = 0V

P/N: PM1738

90

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 81. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level 0.8VCC 0.7VCC 0.8V AC Measurement Level Output timing reference level

0.5VCC

0.2VCC

Note: Input pulse rise and fall time are <5ns

Figure 82. OUTPUT LOADING

DEVICE UNDER TEST

25K ohm

+3V

CL

25K ohm

CL=30pF Including jig capacitance

P/N: PM1738

91

Rev. 1.5, September 26, 2016

MX25L25635F
Table 17. DC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V - 3.6V) Symbol Parameter ILI ILO ISB1 ISB2 Input Load Current Output Leakage Current VCC Standby Current Deep Power-down Current Notes 1 1 1 12 2 Min. Typ. Max. ±2 ±2 50 20 Units Test Conditions uA uA uA uA VCC = VCC Max, VIN = VCC or GND VCC = VCC Max, VOUT = VCC or GND VIN = VCC or GND, CS# = VCC VIN = VCC or GND, CS# = VCC f=133MHz, (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open f=104MHz, (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open f=84MHz, SCLK=0.1VCC/0.9VCC, SO=Open Program in Progress, CS# = VCC Program status register in progress, CS#=VCC Erase in Progress, CS#=VCC Erase in Progress, CS#=VCC

25

mA

ICC1

VCC Read

1

14

20

mA

15 VCC Program Current (PP) VCC Write Status Register (WRSR) Current VCC Sector/Block (32K, 64K) Erase Current (SE/BE/BE32K) VCC Chip Erase Current (CE) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC-0.2

mA

ICC2 ICC3 ICC4 ICC5 VIL VIH VOL VOH

1

14 10

20 12 25 25 0.8 VCC+0.4 0.2

mA mA mA mA V V V V

1 1 -0.5 0.7VCC

14 14

IOL = 100uA IOH = -100uA

Notes : 1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation.

P/N: PM1738

92

Rev. 1.5, September 26, 2016

MX25L25635F
Table 18. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V - 3.6V) Symbol fSCLK fRSCLK fTSCLK tCH(1) tCL(1) Alt. fC fR fT fQ tCLH tCLL Parameter Min. Clock Frequency for all commands (except Read) D.C. Clock Frequency for READ instructions Clock Frequency for 2READ instructions Clock Frequency for 4READ instructions Others (fSCLK) 3.3 Clock High Time Normal Read (fRSCLK) 7 Others (fSCLK) 3.3 Clock Low Time Normal Read (fRSCLK) 7 Clock Rise Time (peak to peak) 0.1 Clock Fall Time (peak to peak) 0.1 CS# Active Setup Time (relative to SCLK) 3 CS# Not Active Hold Time (relative to SCLK) 3 Data In Setup Time 2 Data In Hold Time 2 CS# Active Hold Time (relative to SCLK) 3 CS# Not Active Setup Time (relative to SCLK) 3 Read 7 CS# Deselect Time Write/Erase/Program 30 Output Disable Time Clock Low to Output Valid Loading: 30pF Loading: 30pF/15pF Loading: 15pF Output Hold Time 1 Write Protect Setup Time 20 Write Protect Hold Time 100 CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature Read CS# High to Standby Mode with Electronic Signature Read Write Status/Configuration Register Cycle Time Write Extended Address Register Byte-Program Page Program Cycle Time Page Program Cycle Time (n bytes) Typ. Max. 133 50 84(7) 84(7) Unit MHz MHz MHz MHz ns ns ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us us us ms ns us ms ms

tCLCH(2) tCHCL(2) tSLCH tCSS tCHSL tDVCH tDSU tCHDX tDH tCHSH tSHCH tSHSL tSHQZ
(2)

tCSH tDIS tV tHO

tCLQV tCLQX tWHSL(3) tSHWL(3) tDP(2) tRES1
(2)

8 8 6

10 30 30 40 30 1.5 1.5

tRES2(2) tW tWREAW tBP tPP tPP(5)

40 16 0.5 0.008+ (nx0.004)
(6)

tSE Sector Erase Cycle Time 30 120 ms tBE32 Block Erase (32KB) Cycle Time 150 650 ms tBE Block Erase (64KB) Cycle Time 280 650 ms tCE Chip Erase Cycle Time 110 150 s Notes: 1. tCH + tCL must be greater than or equal to 1/ Frequency. 2. Typical values given for TA=25°C. Not 100% tested. 3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 4. Test condition is shown as Figure 81 and Figure 82. 5. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to program the whole 256 bytes or only a few bytes between 1~256 bytes. 6. “n”=how many bytes to program. In the formula, while n=1, byte program time=12us. 7. By default dummy cycle value. Please refer to the "Table 1. Read performance Comparison".
P/N: PM1738

93

Rev. 1.5, September 26, 2016

MX25L25635F
13. OPERATING CONDITIONS
At Device Power-Up and Power-Down AC timing illustrated in Figure 83 and Figure 84 are for the supply voltages and the control signals at device powerup and power-down. If the timing in the figures is ignored, the device will not operate correctly. During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 83. AC Timing at Device Power-Up
VCC(min) GND tVR tSHSL

VCC

CS#
tCHSL tSLCH tCHSH tSHCH

SCLK
tDVCH tCHDX tCLCH LSB IN tCHCL

SI

MSB IN

SO

High Impedance

Symbol tVR

Parameter VCC Rise Time

Notes 1

Min.

Max. 500000

Unit us/V

Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to Table 18. AC CHARACTERISTICS.

P/N: PM1738

94

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 84. Power-Down Sequence During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.

VCC

CS#

SCLK

Figure 85. Power-up Timing
VCC VCC(max) Chip Selection is Not Allowed VCC(min) tVSL Device is fully accessible

VWI

time

P/N: PM1738

95

Rev. 1.5, September 26, 2016

MX25L25635F
Figure 86. Power Up/Down and Voltage Drop When powering down the device, VCC must drop below VPWD for at least tPWD to ensure the device will initialize correctly during power up. Please refer to "Figure 86. Power Up/Down and Voltage Drop" and "Table 19. Power-Up/ Down Voltage and Timing" below for more details.
VCC
VCC (max.) Chip Select is not allowed

VCC (min.) tVSL Full Device Access Allowed

VPWD (max.) tPWD

Time

Table 19. Power-Up/Down Voltage and Timing Symbol tVSL VWI VPWD tPWD VCC Parameter VCC(min.) to device operation Write Inhibit Voltage VCC voltage needed to below VPWD for ensuring initialization will occur The minimum duration for ensuring initialization will occur VCC Power Supply Min. 800 2.3 300 2.7 Max. 2.5 0.9 3.6 Unit us V V us V

Note: These parameters are characterized only.

13-1. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).

P/N: PM1738

96

Rev. 1.5, September 26, 2016

MX25L25635F
14. ERASE AND PROGRAMMING PERFORMANCE
Parameter Write Status Register Cycle Time Sector Erase Cycle Time (4KB) Block Erase Cycle Time (32KB) Block Erase Cycle Time (64KB) Chip Erase Cycle Time Byte Program Time (via page program command) Page Program Time Erase/Program Cycle 30 0.15 0.28 110 16 0.5 100,000 Min. Typ. (1) Max. (2) 40 120 0.65 0.65 150 30 1.5 Unit ms ms s s s us ms cycles

Note: 1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and all zero pattern. 2. Under worst conditions of 85°C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. The maximum chip programming time is evaluated under the worst conditions of 0°C, VCC=3.3V, and 100K cycle with 90% confidence level.

15. DATA RETENTION
Parameter Data retention Condition 55?C Min. 20 Max. Unit years

16. LATCH-UP CHARACTERISTICS
Min. Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. -1.0V -1.0V -100mA Max. 2 VCCmax VCC + 1.0V +100mA

P/N: PM1738

97

Rev. 1.5, September 26, 2016

MX25L25635F
17. ORDERING INFORMATION
PART NO. MX25L25635FMI-10G MX25L25635FZ2I-10G CLOCK (MHz) 104 104 TEMPERATURE -40°C to 85°C -40°C to 85°C PACKAGE 16-SOP (300mil) 8-WSON (8x6mm) Remark

P/N: PM1738

98

Rev. 1.5, September 26, 2016

MX25L25635F
18. PART NAME DESCRIPTION
MX 25 L 25635F Z2 I 10 G
OPTION: G: RoHS Compliant and Halogen-free SPEED: 10: 104MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: M: 16-SOP (300mil) Z2: 8-WSON (8x6mm) DENSITY & MODE: 25635F: 256Mb

TYPE: L: 3V

DEVICE: 25: Serial Flash

P/N: PM1738

99

Rev. 1.5, September 26, 2016

MX25L25635F
19. PACKAGE INFORMATION

P/N: PM1738

100

Rev. 1.5, September 26, 2016

MX25L25635F

P/N: PM1738

101

Rev. 1.5, September 26, 2016

MX25L25635F
20. REVISION HISTORY

Revision No. Description Page Date 0.01 1. Added Security Register description P68,69 MAY/09/2012 2. Modify the VIH/VIL P94 3. Modify the overshoot from VCC+1.0V or -0.5V to P92 VCC+2.0V or -2.0V 4. Added Fast Boot Sequence P58 5. Modified data retention from 10 years to 20 years P4 6. Added Data Retention P100 7. Corrected content error P9,15,21,23,35,40, P48,50,53-56,59, P70,72,75-77,80,83,90 8. Modified Chip Erase Cycle Time, tCH/tCL and tCLQX P95,100 0.02 1. Modified content and descriptions P7,9,16,19-20,23 AUG/13/2012 P31-32,38, 41-74 2. Modified Min. tVSL from 500us to 800us. P98 3. Modified tCH and tCL from 9ns to 7ns. P95 4. Modified SPB Lock Register table. P74 5. Changed "ADVANCE INFORMATION" to "PRELIMINARY" P4 6. Updated Fast Boot Sequence figures. P59 7. Modified RDSR/RDCR (QPI Mode) figures P29-30 8. Revised lock register bit descriptions P70, 75 1.0 1. Removed "PRELIMINARY". P4 OCT/30/2012 2. Modified 16-SOP pin descriptions. P7 3. Added Enable QPI mode related descriptions. P16 4. Modified Erase Fail bit descriptions. P69 5. Optimize ISB1 & ISB2 spec P94 6. Corrected content error P73,80 1.1 1. Modified RESET Timing definition P90 DEC/26/2012 2. Added Power Up/Down and Voltage Drop information P98 3. Corrected content error P9,57,69,95 1.2 1. Modified RESET Timing definition P83 AUG/09/2013 2. Added USPB information P72,78 3. Added note on WP# setup P39 4. Corrected content error P15,42,57,58,64, P75,77,82-83, P92-93 1.3 1. Updated parameters for DC/AC Characteristics P94,95 OCT/31/2013 2. Updated Erase and Programming Performance P99 3. Content correction P72~78 4. Modified VCC to Ground Potential parameter P92 1.4 1. Updated Package Information P102 AUG/26/2014 2. Description modification P70-79 1.5 1. Updated tVR values P94,96 SEP/26/2016 2. Updated package outline P100,101 3. Description modification P46,51-54,62 4. Modified Note 6 of the SFDP Tables P87

P/N: PM1738

102

Rev. 1.5, September 26, 2016

MX25L25635F
Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright? Macronix International Co., Ltd. 2011~2016. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Au? dio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

103


赞助商链接
相关文章:
更多相关标签: